This Design Idea describes a simple method to create four test devices using an unbuffered CMOS hexa-inverter HD14069UB (Reference 1): a logic pen with a well-defined logic voltage window and an input impedance of about 1MΩ; an open-circuit tester with an upper resistance range from tens of ohms to tens of megohms; a single pulse or pulse train injector or simple signal generator; and a high-impedance audio probe. These test devices can be created using the six inverter gates in a 4069, two or three resistors, and a few passive components.
In a dual-gate CMOS/TTL-compatible probe, the R1 to R4 resistor network biases the inverter input (Figure 1). Because the gate has high input impedance, the values of R1 to R4 are about 100 kΩ to 1 MΩ. The probe tip sinks/sources very little current because R1 to R4 have high impedance, so the probe tip has little effect on the logic level at the test point. Once the input threshold voltage of the gate is known, the required R1 to R4 resistor values can be calculated.
The upper gate detects logic 0, and the lower gate detects logic 1. Set the upper limit to the logic 0 voltage and calculate the values of R1 and R2. Arbitrarily choose R1 = 1MΩ and find a value of R2 so that the voltage at the upper gate input is exactly the threshold voltage. Then R2 = R1 (VT-VL)/ (VS-VT), where VT is the threshold voltage, VL is the logic 0 voltage, and VS is the supply voltage. Similarly, set a lower limit for the logic 1 voltage VT and find a value for R4 according to R3. Choose R3 appropriately, paying attention to the static bias of each gate so that each LED is turned off when the probe is suspended, and you can get the value of R4: R4 = R3VT/(VH-VT).
The probe current is calculated as follows: IP = [-(V-VI)(R3+ R4) + VI (R1+R2)] / (R1+R2)(R3+R4), where IP is the probe current and VI is the voltage at the probe tip. Therefore, for any voltage at the probe tip, the probe impedance is greater than 1MΩ. For 4069 packages with higher threshold voltages (such as 3V), a diode from the positive power rail to the chip followed by a 10kΩ load resistor to ground can help reduce this voltage.
Open circuit testers (Figure 2 and Reference 2) that developers often use are basic test equipment; they are an indispensable piece of equipment on the workbench. An open circuit tester can be made using a gate of a 4069 (with high input impedance and a threshold voltage for the gate output to switch), with an upper limit of the resistance of the test circuit. The total impedance between the probes and the resistance of the switch structure form a voltage divider network that produces a voltage at the input of the gate. When the two resistances are equal, the voltage at the gate input is half the supply voltage. The switching threshold voltage of the gate is also close to half the supply voltage, so the resistance selected for the switch branch sets the approximate open circuit test resistance.
Another useful configuration is to replace the switchable resistor with a variable resistor. This method can set the open-circuit test resistance arbitrarily by adjusting the variable resistor, taking into account the resistance between the probe tips and the heating of the LED. The variable resistor should be set so that the LED is just off. This method results in a compact configuration that can be installed in a small package. Another variable resistor (1kΩ to 2kΩ) is placed in series with the negative probe, allowing an open-circuit resistance test of about 100Ω or less. It is also possible to use a gate with a lower switching threshold voltage by using a pair of diodes followed by a 10kΩ load resistor in series from the positive supply rail to ground. This configuration can also be used to test live AC lines with appropriate modifications (Reference 3), thus making five devices.
Now there are three more gates in the 4069 package, two of which can be used as an astable oscillator/monostable single pulse generator circuit, and a complementary bipolar transistor pair buffer is used to increase the drive current (Figure 3). A SPDT (single-pole double-throw) switch is switched to P (pulse) or A (astable) to select between the two modes. In pulse mode, pressing the switch generates a simple negative-going pulse at the input to the second gate. As C2 begins to charge, the high level obtained at the output of the gate generates a positive-going pulse at the junction of Q1 and Q2. This pulse is also latched, and the switch is debounced by positive feedback through capacitor C1, which begins to charge with a time constant determined by R1, R2, or R3. When the voltage on C1 equals the threshold voltage, the output of the second gate returns to low again through positive feedback from C1, driving the input of the second gate high, ending the pulse.
The diode in parallel with C2 is always reverse biased, and it acts as a very large resistor to discharge C2. Assuming a typical leakage of 1nA for the diode, the equivalent resistance at 2.5V is about 2.5GΩ. The RC discharge time constant of about 125ms is suitable for the speed at which a human hand presses the key.
The values of R1 to R3 set the astable frequency, or one-shot pulse width. The 220kΩ resistor at the second gate input is used to limit the leakage current from the capacitor into the gate input when the gate voltage is below ground, or 0.6V above VDD. The one-shot pulse generates a frequency of approximately 1/(2.2RC), while the threshold voltage of the gate determines the pulse width of the one-shot, which is approximately 0.7RC to 1.1RC.
Sometimes, it is necessary to listen to an audio signal at a certain point in the test circuit. The 4069 has a high input impedance and sufficient output drive current of about 6.8mA to drive a small PCB-mounted speaker. This method can build a simple audio probe (Figure 4). The resistors at the gate input in Figure 4a are used to protect the gate when the voltage of the unit under test is higher than the gate supply voltage.
Figure 4 shows two ways to drive the sound transducer, depending on the loudness required. Figure 4a is a direct connection to a piezoelectric transducer. If the sound is louder, a small resistor can be connected in series with the speaker in Figure 4b to control the volume and prevent possible damage to the speaker or transistor. Figure 4c shows an alternative method to increase sensitivity by biasing the gate input. [page]
The bias voltage is given by the voltage divider network as follows: VB = R2VS/(R1+R2)-R2VL(1-ξ)/(R1+R2)-R2VHξ/(R1+R2), where VS is the supply voltage, ξ is the input signal duty cycle (TH/(TH+TL), assuming a rectangular wave), VH is the logic high voltage, and VL is the logic low voltage. The recommended value for R1 is 1MΩ; the user can select R2 (1MΩ is recommended) based on the bias voltage formula. Many R2 values are possible, as shown in Figure 4c. Capacitor CC (0.1μF is recommended) is connected in series with the signal to be measured to provide a bias voltage in series with the signal. The minimum signal strength is limited by the input threshold window of the gate and has different values for different logic gates. For example, for a rectangular wave signal that switches between zero and the signal voltage, the bias voltage should be below the threshold window, while the sum of the bias voltage and the signal voltage should be above the threshold window.
There is a strict case where both values are at the edge of the window. Therefore, for rectangular signals or attenuated digital signals, VSIG=ΔVT is the minimum required signal strength. Usually, ΔVT is different for different gates; some are wide (CD4069), some are narrow (CD4011). However, when an AC signal (such as a sine wave) is loaded, the negative phase of the signal will reduce the bias strength to VB-VSIG. Therefore, one phase is enough to produce a change equivalent to half the window width. Therefore, for AC signals, the minimum signal strength standard is VSIG=ΔVT/2.
Finally, for an inverting gate, ΔVT = VT2 – VT1, where VT2 is the input voltage at which the gate's output is fully settled at logic 0, and VT1 is the input voltage at which the gate's output is fully settled at logic 1. R1 and R2 help select a signal strength above the set minimum gate threshold window. If R2 is about 1 MΩ, the R2CC time constant is 0.1 seconds, corresponding to 10 Hz, which seems adequate.
For normal digital signals, it is sufficient to ignore R2 and CC. In other words, R2 and CC are equal to zero. It should be noted that this coupler does not compensate for severe signal conditions that would prevent a constant drain current at the output. Its purpose is to provide a typical transistor amplifier bias for the audio probe's gate. The concern for severe signal conditions is accomplished by the 10μF capacitor in series with the gate output in Figure 4b.
Users who prefer to use a traditional AC-coupled RC circuit (with the left terminal of R2 connected to ground rather than the probe tip) can calculate V\'B as a function of several parameters using the following equation: V\'B = VSR2/(R1+R2)-ξ(VH–VL)–VL, where all terms have their usual meanings.
Compare this to the previous equation. In the V\'B equation, the bias voltage is dependent on VH or VL through a single product factor of the duty cycle, while in the bias voltage equation, it depends on another product factor R2/(R1+ R2)<1, thus reducing the dependency and producing a flatter data curve with duty cycle, as shown in Figure 5, with a rectangular wave of VL/VH=0/4V and a varying duty cycle.
All of these small devices can be put in a small container, such as a hose, and probed to perform various tests (Reference 4). The probe power supply can be two 3V CR2032 lithium batteries; the CMOS4069 is a low-power device. However, it should be noted that the thresholds of 4069 devices vary greatly from manufacturer to manufacturer, so the values should be checked when selecting the device to make the test equipment, especially for the first three devices.
The key to these test devices is the high input impedance of the CMOS gates. Other packages (such as CD4011/4001) can also make multiple devices, because the key is to use inverting gates.
Editor's Note: In all the circuits discussed here, the probe ground should be connected directly to the ground of the device under test. Although the design example does not discuss this, some readers may want to add CD4011/4001NAND/NOR logic to combine the open circuit tester, monostable oscillator and audio probe to provide an audible open circuit tester.
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Recommended ReadingLatest update time:2024-11-16 15:58
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