How to Improve FPGA-PWM Counter Performance by Swapping Bits

Simply changing the FPGA counter specifications can reduce the ripple of the PWM counter as a DAC function. When some analog output is required and an FPGA is available in the system, it is likely to choose to use a PWM module and a simple low-pass filter as shown in Figure 1. The output of the FPGA is a fixed frequency, and the counter and digital comparator make the duty cycle variable. Typical waveform (Table 1).

Figure 1 PWM module and simple low-pass filter

Table 1 Typical waveform of FPGA output

Assuming a high signal enable, the counter counts every clock cycle and the frequency of the PWM output is the clock frequency divided by a power of 2. By connecting a prescaler, the enable is used to reduce the output frequency. Since the output frequency is fixed, the filter is easy to calculate. It is known that the worst ripple occurs at a duty cycle of 50%. The maximum ripple and rise time constraints combine to determine the filter type and RC (resistance/capacitance) value.

A non-trivial modification to the code in Table 1 can improve the performance of the PWM circuit. Whereas in the original system the maximum ripple current occurred at 50% duty cycle and the minimum ripple current occurred at minimum duty cycle, the improved version shows the maximum ripple equal to the minimum of the standard version. The key is to generate the highest frequency possible while keeping the average duty cycle constant. The higher the output pulse frequency, the better the filter performance. Table 1 is modified by reprogramming the binary comparators by swapping all the bits from left to right. The MSB (most significant bit) becomes the LSB (least significant bit), the LSB becomes the MSB, and so on (Table 2). Only bits need to be reprogrammed, no additional registers or logic cells are needed.

Table 2 FPGA-PWM reprogrammed binary comparator

Table 3 shows the pulse sequence from the 4-bit PWM. In Table 3, we can see that the frequency is the highest at 50% duty cycle (second column, value 8), which is the clock frequency divided by 2. At the first ripple point (second column, value 1), the same ripple occurs in the traditional PWM system, that is, the pulse sequence is the same.

Table 3 Pulse sequence issued by 4-bit PWM