Design of a simple storage oscilloscope based on FPGA

introduction

Although traditional oscilloscopes are fully functional, their applications are limited by a series of problems such as large size, heavy weight, high cost, etc. In view of this, portable digital storage collectors came into being. They use new technologies such as LCD display, high-speed A/D acquisition and conversion, and ASIC chips. They have strong practicality and huge market potential, and also represent a development trend of contemporary electronic measuring instruments, that is, the development towards handheld instruments with multiple functions, small size, light weight, and easy use.

System structure and working principle

The hardware part of the system is a high-speed data acquisition circuit board. It can realize dual-channel data input, and the sampling frequency of each channel can reach 60Mbit/s. From the functional point of view, the hardware system can be divided into: signal front-end amplification and conditioning module, high-speed 模数转换\'); companyAdEvent.show(this,\'companyAdDiv\',[5,18])"> analog-to-digital conversion module, FPGA logic control module, single-chip control module, USB data transmission module, LCD display and keyboard control, etc. Its structure is shown in Figure 1.

Figure 1 System principle structure diagram

After the input signal is converted by the preamplifier and gain adjustable circuit, it becomes the input voltage that meets the requirements of the A/D converter . The digital signal after A/D conversion is cached by the FIFO in the FPGA and then transmitted to the computer through the USB interface for subsequent data processing, or directly controlled by the microcontroller to display the collected signal on the LCD screen.

High-speed data acquisition module

This system can realize dual-channel synchronous data acquisition, and each channel

The acquisition speed should reach 60Mbit/s. Considering that the two-way data acquisition should be synchronized and parallel, each channel has its own sample-and-hold device and A/D converter in the design. The MAX1197 A/D converter from MAXIM is selected. It is a dual-channel, 3.3V powered analog-to-digital converter chip with a sampling frequency of 60Mbit/s per channel. It integrates a dual-channel differential broadband sample-and-hold device and an A/D converter, can output latch, and has the characteristics of low power consumption, small size, and high dynamic performance.

The measurement voltage range of this system can reach ±300V. The input signal is first attenuated by 1:1, 10:1 or 100:1 using an oscilloscope probe and voltage division on the circuit board, and then processed by subsequent circuits to meet the input voltage range requirements of the A/D converter.

The output signal obtained by the measured signal through the universal probe and the voltage divider needs to be transformed into a low output impedance to maintain the integrity of the signal due to the high 输出阻抗\'); companyAdEvent.show(this,\'companyAdDiv\',[5,18])"> output impedance . At the same time, for a system, overload is inevitable. In the case of overload, if there is no protection, the device is easily damaged. Therefore, an overload protection circuit composed of a diode and a resistor is designed in the system to limit the input signal to the range of ±4.8V. For impedance transformation, the high-performance FET input single voltage feedback amplifier AD8065 chip of ADI is selected to form a follower to realize impedance transformation. The signal after impedance transformation must also be adjusted by gain. In order to make the voltage input to the A/D converter meet the input voltage requirements of the A/D, an analog switch and a broadband precision amplifier are used. Different access resistance values ​​are selected by the analog switch to achieve different amplification factors and achieve the purpose of programmable amplification. The gain adjustment circuit is shown in Figure 2, and the input protection and impedance transformation circuit is shown in Figure 3.

Figure 2 Gain adjustment circuit

Figure 3 Input protection and impedance conversion circuit

FPGA control unit

Programmable logic device FPGA is a semi-customized ASIC that allows circuit designers to program and implement the functions of specific applications. This design uses two different methods: schematic input and VHDL language input. The control unit carries most of the control tasks and provides corresponding control signals for each functional module to ensure the correctness of the entire system. The following functions are implemented:

Frequency division circuit and generation of control signal for A/D converter

This data acquisition system has a relatively wide measurement range. A frequency division circuit is designed inside the FPGA to select different sampling frequencies for the measured signals of different frequencies, ensuring that the collected data is more accurate. The frequency division unit uses a graphical input method to implement its internal structure as shown in Figure 4. In Figure 4, when the input of the T trigger is 1, the output will jump when each clock edge arrives to achieve frequency division. At the same time, we can see that the input of the T trigger is composed of some logical combinations, which constitutes a gated clock. For the gated clock, carefully analyze the clock function to avoid the influence of glitches. When the gated clock meets the following two conditions, it can ensure that the clock signal does not have dangerous glitches, and the gated clock can work as reliably as the global clock. [page]

The logic driving the clock must contain only one AND gate or one OR gate. If any additional logic is used, glitches caused by contention may occur in certain operating conditions.

One input of the logic gate acts as the actual clock, and all other inputs of the logic gate must be treated as address or control lines that obey setup and hold time constraints relative to the clock.

For the A/D converter in this design, there are only two control signals: clock input signal CLK and enable output signal OE. The CLK signal directly inputs the 60M signal through the active crystal oscillator, while the OE signal is obtained by inverting the clock signal with the same frequency and phase as CLK inside the FPGA, which just meets the conversion timing relationship of the A/D converter.

Figure 4 Internal structure of the frequency division circuit

Figure 5 Frequency division circuit and frequency selection circuit symbol diagram

The frequency division circuit, frequency selection circuit and control signal generation circuit of the A/D converter generate corresponding logic symbols at the top level as shown in FIG. 5 .

FIFO functional unit design

The A/D sampling rate of this system is relatively high, with a sampling period of 16.7ns. However, the selected Winbond microcontroller 77E58 has a read and write period of 100ns at a crystal oscillator of 40MHz, and the bus transmission rate is relatively low, so the two cannot match in speed. In this case, it is necessary to establish a corresponding buffer path between high-speed acquisition and low-speed processing to ensure the normal operation of the system. For this reason, a first-in first-out buffer (FIFO) is added between the A/D converter and the microcontroller processor to alleviate the interface contradiction between high-speed signals and low-speed devices. In this design, the EAB ( embedded logic block) in EP1K50QC208 is used to directly generate two 512*8-bit FIFOs through the LPM tool in Quartus II as data buffers for two A/D converters. The graphic symbol generated in Quartus II and its timing waveform are shown in Figure 6. The input signals of FIFO include data input signal, which is directly connected to the input of A/D converter; write signal and write enable signal, which are connected to the above frequency selection signal, and can write data to FIFO at a suitable rate, and write enable is set to be always valid; read signal and read enable signal, which are given by control signals sent by microcontroller; asynchronous clear signal clears FIFO before each write. Output signals include data signal, which is connected to the data line of microcontroller to transmit data; full flag signal, which stops writing to FIFO when valid; empty flag signal, which stops reading from FIFO when valid.

Figure 6 FIFO graphic symbol and its timing waveform

Figure 7 Symbol diagram of the frequency measurement module

Frequency measurement module design

Figure 8 Dual-channel waveform display

The frequency measurement module plays a very important role in this system. It not only determines the sampling frequency, but also determines the basic time base of the LCD screen . The measurement frequency is actually the count per unit time. In this design, the specific design idea of ​​the frequency measurement module is: first, the data converted by the A/D converter is passed through a comparator to obtain the frequency measurement pulse. Since the A/D in this design converts the 0V voltage into 0x80, in order to avoid the frequency measurement error caused by the small signal oscillation near 0V, the fixed comparison value of the comparator is set to 0x88. Then the frequency measurement pulse is synchronized through a D trigger and counting begins. In the counting process, in order to avoid the influence of sharp pulses or burr signals on the counting, the appropriate filtering pulse width is selected according to the result of the last frequency measurement, that is, the signal pulse smaller than the given pulse width will not be counted, which improves the accuracy of the entire measurement. The symbol diagram of the entire frequency measurement module is shown in Figure 7. In Figure 7, compare is a comparison module, and then after trigger synchronization, it passes through the pulse width filter module (FreLatch1) and then reaches the counting frequency measurement module (MeasureFrequency). The measured data is output through the eight-bit registers counter_out1, counter_out2 and counter_out3. The OneSecondPulse module is a module that generates a 1s pulse and provides a reference pulse for counting. [page]

LCD display and keyboard module

In this design, we choose the LCD display module MS320240B with built-in SED1335 controller, with a resolution of 320*240. It can not only display text or graphics separately, but also display graphics and text in a composite way. In this system, the waveform of the measured signal, the voltage value and time value of the intersection of the two cursors and the waveform can be displayed on the LCD screen. The display on the LCD screen is shown in Figure 8.

Among the single-chip communication input devices that realize the human-computer communication function, the simplest is a keyboard composed of a switch matrix composed of keys, which can issue various control commands and input data at any time. Usually, the keys are mechanical switches, which have many disadvantages. The main one is that there will be a slight jitter when the key is pressed or popped up. The jitter time is related to the mechanical characteristics of the switch, generally 5ms~10ms. In order to avoid scanning the keyboard during the jitter period to obtain incorrect row and column values, it is generally delayed for 10ms after detecting that a key is pressed before scanning. In this design, a 3*8 determinant keyboard is used to issue various commands to operate the collector similar to the oscilloscope button.

Figure 9: The host computer control panel of the simple oscilloscope

USB Communication Unit

This design uses Cypress's CY7C68013 chip to implement the design of the USB transmission module. CY7C68013 is a chip that complies with the USB2.0 standard. The collected data is transmitted to the computer in real time through the USB bus , so that the host computer can also display the waveform in real time and store data very conveniently.

Host computer application design

In the host computer, the powerful computing power and graphic environment of the computer are used to establish a graphical soft panel to replace the conventional instrument control panel. The soft panel has switches, indicator lights and other control components similar to the actual instrument. The user operates the soft panel with a mouse or keyboard to check the performance and operability of the instrument. At the same time, the user can perform tests and measurements without writing test programs, realizing the automation and intelligence of the test.

In this design, LabVIEW is used to write the host computer application program. The host computer control panel of the simple oscilloscope is shown in Figure 9, which mainly realizes the dual-channel waveform display function. The display panel uses cursors to measure voltage and time, which can reduce human reading errors and improve measurement accuracy. When two channels are displayed at the same time, the parameters of the channel to be displayed can be selected through the "Current Channel Selection" button on the front panel. The RUN/ST OP button can start and stop the data acquisition display module, which is convenient for operation and reading. The front panel also has drag and zoom buttons for easy viewing of graphics.

Conclusion

This article is the hardware/software design ideas and design scheme of a simple digital oscilloscope system based on FPGA . After the design of this system is completed, the test shows that the system can convert the collected data into the corresponding waveform display through software program control. The displayed waveform is basically consistent with the waveform of the input signal. It can realize the basic functions of portable acquisition systems such as data acquisition, caching, transmission and waveform display, and has a very broad application prospect.