USB3.0 physical layer test introduction and difficulty analysis

USB Introduction
USB (Universal Serial Bus) is used to connect peripheral devices such as keyboards, mice, printers, scanners, digital cameras, MP3, USB flash drives, etc. to computers. It standardizes the interface between computers and peripheral devices. Since 2000, computers and devices supporting USB 2.0 have been widely used. USB 2.0 includes three speeds: high speed 480Mbps, full speed 12Mbps, and low speed 1.5Mbps. Currently, except for keyboards and mice, which are low-speed devices, most devices are high-speed devices with a speed of 480M.

Although the speed of USB2.0 is quite fast, it is still a bit slow for the current high-definition video and TB-level data transmission. In November 2008, HP, Intel, Microsoft, NEC, ST-NXP, and TI jointly released the V1.0 specification of USB3.0. USB3.0 is also called Super Speed ​​USB, with a bit rate of up to 5Gbps, which is more than 10 times higher than the current 480Mbps rate of USB2.0. To quote Intel expert Jeff Ravencraft: "For example, a 25GB file transfer takes 14 minutes with USB2.0, while 3.0 only takes about 70 seconds (as shown in Figure 1)." 25GB is exactly the capacity of a single-sided single-layer Blu-ray disc. USB3.0 is expected to be gradually used in computers and consumer electronics in 2011.

Figure 1: Speed ​​comparison between USB 2.0 and USB 3.0

LeCroy released the USB 3.0 physical layer test solution in April 2009, which can provide end-to-end interoperability and compatibility testing, including transmitter testing, receiver testing, and TDR testing. In addition, LeCroy also provides the industry-leading USB 3.0 protocol layer test solution.

Introduction to USB3.0 physical layer test content
For most high-speed serial signal measurements, transmitter measurement and receiver measurement are usually included, also known as TX measurement and RX measurement. At present, hardware engineers who design at the board level are already very familiar with transmitter testing. Usually a high-bandwidth oscilloscope plus a test fixture or a differential probe is used for measurement. The test items are mainly eye diagrams, jitter, rise/fall time, amplitude, etc. The location of the probe point is generally the transmitter or receiver of the serial link. Since the signals measured are sent by the high-speed transceiver chip, this type of test is usually called a transmitter test. Figure 2 below is a schematic diagram of a typical TX test.

However, some engineers mistakenly believe that measuring eye diagrams or jitter near the link receiving end is receiver measurement. This is mainly because in the past, receiver testing was not a mandatory test item in board-level hardware development, which caused some misunderstandings. However, in high-speed transceiver chip-level hardware development, receiver testing is a must. [page]

Figure 3 is a schematic diagram of receiver testing. The instrument required for receiver testing is a bit error rate tester (BERT for short). BERT usually includes two parts: a pattern generator and an error detector. During receiver testing, the pattern generator outputs a signal with a specific pattern and a lot of jitter and noise to the RX of the product under test (PUT for short). After receiving it, the PUT obtains a bit stream of 1 and 0 through the clock and data recovery circuit (CDR for short), the discrimination circuit and decoding, and then loops back to the output register and sends it out from the TX buffer of the PUT. The TX of the PUT is connected to the error detector of the BERT. The CDR and discrimination circuit in the error detector process and decode to obtain a data bit stream of 1 and 0, which is then compared with the specific pattern data output by the pattern generator. If the two are completely consistent, there is no error. Otherwise, the number of errors and the total number of bits of the received code stream are recorded. The former divided by the latter is the error rate. At the same time, the jitter value of the signal output by the pattern generator when the error is received is recorded. If the eye diagram of the signal received at the RX end of the PUT is measured with an oscilloscope, it is usually closed, as shown in the lower left figure of Figure 3; if the eye diagram of the signal output at the TX end of the PUT is measured with an oscilloscope, it is usually a good eye diagram, as shown in the lower right figure of Figure 3. By modifying the random jitter, inherent jitter, signal amplitude and other parameters of the output signal of the pattern generator, the receiver performance of the PUT can be quickly evaluated.

LeCroy's USB3.0 physical layer test solution includes: oscilloscope SDA813Zi, bit error rate tester PeRT, USB3.0 test fixture, automated test software QualiPHY-USB3 and eye doctor software.

LeCroy's latest version of the consistency test software QualiPHY-USB3 is developed based on the USB3.0 Electrical Compliance Test Specification Rev0.9 released in November 2009, and is constantly updated as the test specification is updated. The software is installed on an oscilloscope, which is connected to PeRT3 via a USB cable and communicates with PeRT3 using a USB cable. During the test, QualiPHY software can control PeRT3 to send specific signals or read RX test results from PeRT3, so that only QualiPHY software is needed to complete all TX and RX tests. The following test items are included in the QualiPHY-USB3 test software:

1. LFPS (Low Frequency Periodic Signaling) signal measurement

2. SSC (Spread Spectrum Clock) measurement

3. Jitter and eye diagram measurements

4. AC and DC common mode voltage measurements

5. Differential voltage amplitude and de-emphasis measurement

6. Bit error test and jitter tolerance measurement

Among them, the first five items are transmitter tests, and the last item is receiver test.

Difficulties in USB3.0 physical layer testing
There are the following difficulties in USB3.0 physical layer testing

1. Multiple test patterns are required to complete all TX test items. Some non-USB3.0 chip developers find it difficult to make the PUT send specific compatibility test patterns.

2. During receiver testing, it is difficult for the PUT to enter loopback mode

3. During receiver testing, the bit stream sent by the PUT will add some SKP. In this way, the data received by the BERT Error Dector includes the test pattern and some SKP. Compared with the test pattern sent by the pattern generator, the traditional BERT will mistakenly think that it has measured a bit error. [page]

Difficulty 1:

The USB3.0 specification defines a variety of compliance test patterns (CP for short), including nine test patterns from CP0 to CP8 as shown in Figure 4. In TX measurement, four patterns, CP0/CP1/CP7/CP8, are required: CP0 is used for eye diagram, jitter, and common mode voltage measurement; CP1 is used for SSC spread spectrum measurement and random jitter measurement; CP7 is used for de-emphasis measurement; and CP8 is used for differential voltage amplitude measurement.

For engineers in board-level development, it is difficult to make PUT send different test patterns without the package sending program provided by IC manufacturers. LeCroy's USB3 test solution can solve this problem. As shown in Figure 5, PUT is connected to the USB3 fixture, TX is output to the oscilloscope, and RX is connected to the signal output terminal of PeRT. Usually, PUT will send CP0 pattern after power-on, and the oscilloscope controls PERT through the USB cable. Then PeRT will send a Ping.LFPS command to PUT. After PUT receives 1 Ping.LFPS, the output pattern switches to CP1. After the oscilloscope captures the CP1 pattern, it controls PERT to send another Ping.LFPS, and the output pattern of PUT switches to CP2, that is, PUT outputs the next CP every time it receives 1 Ping.LFPS (the next pattern of CP8 is CP0). By controlling PERT with an oscilloscope, PERT controls PUT to send different CPs, and all TX test items can be completed.

Difficulty 2:

In receiver testing, the process of Polling.LFPS->Rx.EQ->TS1->TS2->Loopback is required to enter the loopback mode to measure receiver performance. In this process, the receiver test instrument (such as BERT) needs to continuously "handshake" with the PUT, communicate with the PUT at the link layer, and make it enter the Loopback mode step by step. This is very difficult for some receiver test instruments. For example, the receiver test instrument of Company X is a traditional BERT, which cannot "handshake" with the PUT, and it is difficult to gradually enter the Loopback mode from Polling.LFPS. The receiver test instrument of Company Y is an arbitrary waveform generator, which can send LFPS signaling to the PUT, but cannot identify the signaling of the PUT response from the protocol. Therefore, it is difficult to gradually enter the Loopback mode from Polling.LFPS. If the loopback mode is not entered, the user will usually edit the script on the signal source and constantly adjust the time intervals between LFPS, Rx.EQ, TS1, and TS2, hoping that the adjusted signaling can gradually make the PUT enter the loopback mode. When measuring the new USB3.0 IC, the signal source output script may need to be modified. We call this method of sending but not receiving blind handshake, that is, the receiver tester blindly sends signals to "shake hands" with the PUT, but cannot recognize the signaling responded by the PUT.

LeCroy's USB3.0 receiver tester PeRT solves the problem of difficulty in entering loopback mode. PeRT, which stands for Protocol-enabled Receiver and Transmitter Tolerance Tester, has the link layer protocol analysis capability, can smoothly "shake hands" with the PUT, gradually enter the Loopback mode, and quickly measure the receiver. [page]

Difficulty 3:

In USB3.0, the reference clock frequencies of the products at both ends of the link may be different. The reference clock allows an accuracy of +/-300ppm. The frequency deviation introduced by SSC spread spectrum is 0 to -5000ppm, so the total frequency deviation is between -5300ppm and 300ppm. In order to compensate for the frequency deviation, two SKPs (i.e., K28.1 codes) are inserted into the data stream of USB3 for every 354 symbols. The receiver needs to be able to identify and delete SKPs. In the USB3.0 chip, adding and deleting SKPs is implemented by the Elasticity Buffer (see Section 6.4.3 of the USB3.0 Specification for details). Therefore, when testing the receiver, some SKPs will be added to the bit stream sent by the PUT. The data received by the error detector includes the test pattern and some SKPs. Then, when comparing the test pattern sent by the pattern generator, the traditional BERT will mistakenly think that a bit error has been measured. However, LeCroy's PeRT can intelligently add and delete SKPs before calculating whether there is a bit error. FIG6 is a schematic diagram of the USB 3.0 Elasticity Buffer processing SKP.

Features of LeCroy's USB3 test solution
In November 2009, LeCroy updated the physical layer test solution for USB3.0, which can automatically complete all items of compatibility testing. As shown in Figures 7 and 8 below, the LeCroy USB3.0 solution diagram, the test equipment and accessories are composed of an oscilloscope with a bandwidth of more than 13GHz, PeRT3, RF Switch, USB3.0 test fixture, etc.

During the TX test, the signal transmission link is shown in the upper part of Figure 7. The LeCroy oscilloscope controls PeRT3 through a USB cable, and PeRT3 sends Ping.LFPS to the RX end of the PUT through a coaxial cable. The TX of the PUT is connected to the channel of the oscilloscope. Every time the PeRT sends Ping.LFPS, the code pattern sent by the TX of the PUT switches between CP0 and CP8 (for example, from CP0 to CP1, or from CP8 to CP0). In this way, the tester does not need to configure the PUT to send different test code patterns. Through PeRT3, LeCroy's QualiPHY software will automatically control the PUT to send different test code patterns to complete all TX tests.

During the RX test, the oscilloscope controls the RF Switch to switch to another link through the GPIB interface. As shown in the lower part of Figure 7, the jittered signal output by the PeRT3 pattern generator first passes through the Compliance Test Channel (consisting of Intel's 11-inch backplane and a 3-meter USB3.0 cable), then connects to the USB3 fixture, and enters the RX end of the PUT. The TX end of the PUT passes through the fixture and sends the signal to the Error Dector end of the PeRT3.

Since the oscilloscope controls the PeRT and reads the test results of the PeRT through the USB cable, and automatically switches between links by controlling the RF Switch through GPIB, the TX and RX tests of USB3.0 are fully automated without manual intervention. The operation steps are very simple, saving test time.

Conclusion
This article briefly introduces the physical layer test content and test difficulties of USB3.0. LeCroy's consistency test software QualiPHY-USB3.0 can control the oscilloscope and bit error rate tester PeRT3, quickly and automatically measure all USB3.0 test items, greatly simplifying the test and debugging time of engineers. It is the most comprehensive and fast test solution in the industry.

References
1, Universal Serial Bus 3.0 Specification, Revision 1.0.
2, Electrical Compliance Test Specification Rev0.9, SuperSpeed ​​USB.
3, LeCroy USB3.0 Datasheet.