Testing the SDRAM controller's PDMA

1 Introduction

Modern electronic information equipment often needs to store and process a large amount of digital information. A high-performance memory controller can greatly improve the performance of the system. When designing an SDRAM controller, many factors need to be considered. After the design is completed, multiple tests must be performed to see whether the required performance is fully met. For this reason, we designed a PDMA (Programmable Direct Memory Access) to test the performance of the SDRAM controller. In SoC, the SDRAM controller often exchanges data with multiple IP modules (graphics processing unit, audio processing unit, etc.). Using multiple PDMA channels to access memory simultaneously can truly simulate the situation where the SDRAM controller is randomly accessed by multiple IPs in the SoC environment.

2 Structure and working principle of PDMA

PDMA is the abbreviation of programmable direct memory access. Figure 1 The virtual box is the internal module structure of PDMA, which is mainly composed of two parts: register group and controller. The register group is used to save configuration parameters and status information after PDMA accesses the SDRMA controller and receive, start, stop and other control information. Figure 2 is the internal structure of the PDMA register group.

The register group module contains a synchronization module, control register, status register and register groups of each channel. The register group of each sub-channel contains three registers, namely, access base address register, access mode register and cycle counter. The functional description of each register is shown in Table 1.

The PDMA controller mainly consists of four parts: a state machine for generating write data, an address decoding module, a FIFO and a read data verification module. The structure of each PDMA controller is shown in Figure 3. Its core logic is a state machine. We use a two-layer nested state machine to implement the control function, as shown in Figure 4.

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3 Structure and working principle of the test system

In this design, PDMA is used to simulate multiple IP cores to read and write to the SDRAM controller to verify whether the design of the SDRAM controller is efficient and reasonable, and whether the performance is stable.

The entire PDMA test system consists of three parts: the PCI interface module, PDMA, and SDRAM controller (see Figure 1). The PCI interface module and PDMA are connected by an internal IO bus. The PDMA and SDRAM controller are connected by an internal Memory bus. The PCI interface module connects the external PCI bus and the internal PDMA, converts the PCI IO access initiated by the external to configure the PDMA parameters and read and write the command, status and other registers. After obtaining the configuration parameters and the command information to start the access, the PDMA starts accessing the SDRAM controller (write and then read), and reflects the test results in the PDMA status register. The

specific working process of the test PDMA is as follows:

(1) The PCI interface module configures the parameters of each PDMA channel (such as access length, access base address, access mode, etc.);

(2) The PCI interface module writes the PDMA control register to start reading and writing to the SDRAM;

(3) The PCI interface module reads the PDMA status register to detect whether the access is completed. If completed, it reads the status information after completion (such as error bit, address where the error occurred).

4 RTL simulation

After completing the RTL level design, we used Cadence's simulation tool VerilogXL to perform functional simulation of the design. The simulation environment is based on PCI, so the simulation sequence is as follows:

(1) Configure the IO Base and Memory Base registers of the PCI configuration space;

(2) Write to the PCI configuration space 54H, 58H and other registers to configure the parameters of the SDRAM controller and SDRAM chip;

(3) Write the command register of the PCI configuration space (offset==04h) to enable the device;

(4) Access the PDMA configuration registers in the PCI IO space to set the configuration parameters of each PDMA channel;

(5) Write the corresponding command to start PDMA access to the new internal SDRAM controller;

(6) Check the status register of PDMA and exit the simulation program according to the set conditions (normal end or error);

(7) Open the waveform file and check if any error occurs.

Figure 5 is a simulation waveform of a write IO register access initiated by PCI. The configuration data of PDMA is completed through several such operations.

Relatively speaking, we are more concerned about how PDMA accesses Memory. Figure 6 shows the access timing in write/read mode initiated by a PDMA. The signal of GROUP1 is the internal Memory bus signal group initiated by PDMA, while the signal of GROUP2 is the bus protocol between the Memory controller and the memory chip that complies with the JEDEC standard. From the figure, we can clearly see the conversion process of the bus protocol and promptly detect whether there is any violation of the protocol.

5 Method and process of board testing

After completing the functional simulation, the design is synthesized using the Synopsys synthesis tool FPGA compiler, and the VERTEX1600E series of XILINX is selected as the target device to generate the corresponding netlist file and download it to the FPGA for testing. The results of the synthesis are shown in Table 3. The test platform is a PC with a test card with a PCI standard interface and PCI read and write software. The board test process is as follows:

(1) Download the bit file to the FPGA;

(2) Configure the SDRAM controller;

(3) Set the PDMA register;

(4) Start PDMA access;

(5) Read back the status bit of PDMA.

The corresponding test vector needs to be input during the test. A good software interface can greatly reduce the workload of hardware engineers in writing and inputting test vectors. Table 4 shows the content and results of a test vector. Tests like this need to be performed multiple times to improve fault coverage and comprehensively monitor the performance of PDMA.

6 Experimental conclusions

After continuous debugging and improvement, PDMA can accurately initiate memory access according to the configuration of the function register and can report the operation errors of the SDRAM controller in a timely manner. This test platform is not only suitable for verifying the design of SDRAM controllers, but also can be configured to support the test verification of DDR memory controllers with better performance after very small changes. The flexible configuration method makes it a universal test platform. To test different memory controllers, it is only necessary to configure the corresponding configuration registers with software. The hardware basically does not need to be changed, which greatly saves design time and improves the success rate and efficiency of the design.