Realization of Virtual Test System Based on FPGA

1 Introduction

Traditional test and measurement instruments have problems such as high price, large size, low data transmission rate, and difficulty in storage and display. This paper uses FPGA to realize data processing and logic control, makes full use of PC, and combines the Labwindows graphical upper-level application software interface to generate a virtual test system with strong competitiveness. Under the control of the FPGA single-board single-chip master device, this system realizes two independent, amplitude-controllable signal generators, one virtual storage oscilloscope, and a 16-channel high-speed logic analyzer with external trigger signal and sampling clock.

2 Hardware Design

2.1 Hardware System Block Diagram

The hardware system design is based on the low-end FPGA single-chip EP1C6 with strong parallel processing capabilities and reconfigurability as the main control device. Figure 1 shows the hardware system block diagram, which consists of a reference voltage and selection module, a USB2.0 interface module, a power design module, a high-speed storage module, an oscilloscope conditioning input A/D conversion module, a logic analyzer matching input comparison module, and a signal source output filter module.

The USB2.0 interface module is used to cooperate with the application software to accept commands from the host computer and return collected data. Cypress's CY7C68013 USB2.0 device device is used, and the enhanced 8051 inside the device controls data transmission. By downloading the firmware code to configure the 8051, the device device simulates the action of the main control FPGA as an off-chip slave FI-FO, reducing the difficulty of FPGA design. The voltage reference selection module can provide reference voltage for the signal source D/A, comparator and oscilloscope A/D. Considering the switching between multiple measurement functions and the possibility of simultaneous operation, two-way reference voltage output and reference voltage path selection modules are used to realize the modes of independent operation of dual-channel signal sources, single-channel signal source working with oscilloscopes, and single-channel signal source working with logic analyzers.

2.2 Dual-channel signal source design

Using the internal M4K storage module, logic resources and high-frequency clock of the FPGA, the dual-channel signal source is realized with DDS/control module + high-speed D/A, avoiding the use of dedicated DDS devices, thereby saving costs and improving the diversity of functions. The front-end module of the dual-channel signal source circuit design includes a sine wave with variable amplitude and phase realized by DDS mode, and a square wave, triangle wave, modulated waveform and other data outputs with adjustable duty cycle expressed in hardware language; the back-end includes an analog-to-digital conversion module composed of a high-speed D/A converter DAC2900 (as shown in Figure 2) and a signal conditioning circuit (as shown in Figure 3), in which the conditioning module is mainly composed of a strong drive module and a third-order π-type low-pass network with a cutoff frequency of 35 MHz.

2.3 Design of high-speed logic analyzer and storage oscilloscope

The sampling rate of the high-speed logic analyzer is 150 MHz. For 16-channel sampling, the data volume reaches 150 M×16 bit. Two 10 ns-level 256 K×16 bit RAMs are used to expand the data bits and realize the reduced speed storage. The number of bits is expanded by 1 times, and the storage rate is reduced by 1 times. For the storage speed of 75 MHz, Cypress's CY7C-1041-8ns is selected. The RAM data address line and the logic analyzer comparator interface are connected to the FPGA, and the RAM interface and the storage oscilloscope are multiplexed.

The design of the virtual storage oscilloscope is realized by front-end conditioning and high-speed A/D sampling device TLC5540. Figure 4 shows the front-end conditioning circuit of the oscilloscope, which includes three parts: clamping circuit, amplification and attenuation network and power amplifier. The clamping circuit mainly clamps the input voltage to the input range of the back-end A/D to prevent circuit damage. Observe the clamping waveform through the oscilloscope and turn on the attenuation network. Conversely, if the signal is too small, turn on the amplification network to achieve high amplitude bandwidth. The purpose of the power amplifier circuit is to improve the signal driving capability and measurement accuracy.

3 Board Logic Design

3.1 Control Logic Implementation

SOPC (System on Programmable Chip) technology was first proposed by Altera in 2000, providing a way to implement SOC functions using large-scale programmable devices FPGA. The introduction of SOPC brings an effective solution to SOCs that are only used in small batches or are in the development stage. With the NIOS II soft-core processor provided by Altera, an efficient SOPC system is generated to realize board control design, simplifying data communication and coordination between modules. Figure 5 details the composition of the SOPC system.

As can be seen from the figure, the Avalon bus is the bridge of the entire system. The Avalon interface specification is designed for the development of peripherals in the SOPC environment of the programmable system on chip. It provides the designers of peripherals with the basis for expressing the address-based read/write interface in the master peripheral and the slave peripheral, and is an important part of the SOPC hardware system.

The Nios II processor soft core supports interrupt exceptions and user-defined instruction sets, fully supports C language, and can write user logic interfaces to implement a simplified, non-redundant dedicated Nios II processor system. The host computer instructions can be sent to the soft processor completely in the form of strings through the USB interface module. The Nios soft core implements command parsing through programming, and responds to output at the same time, configures each peripheral, completes the specified job according to the command, and returns data. The soft core inside the FPGA is connected to the external device through GPIO to form the entire system. The advantage of the Nios II soft core processor is that the command parsing and the Avalon peripheral bus bit width match, and the SOPC system can efficiently complete the control transmission of the logic analyzer and oscilloscope. However, its data transmission is slightly insufficient at high speeds and becomes a system bottleneck, mainly due to the C language instruction set. As for the logic analyzer, oscilloscope and RAM interface for high-speed acquisition and storage, the read and write rate is higher than 100M, realizing high-speed acquisition channel and providing simple start acquisition, acquisition end, data full and other signals to the bus as a peripheral connected to Nios soft core, which is the key to improving the measurement system parameters. Based on Nios soft core, the high-speed interface module of this system is implemented by Verilog HDL language and FPGA internal resources, that is, the off-chip high-speed reading control module.

3.2 FPGA implementation of improved low resource consumption rate DDS

This system realizes dual-channel completely independent DDS signal source based on FPGA. The hardware design constitutes the third part of the DDS technology implementation. The design details of the first two parts, phase accumulator and lookup table ROM, are shown in Figure 6.

The FPGA design and implementation of a single-channel DDS mainly includes a phase accumulator address generation and control module, a waveform storage and type selection module. The phase accumulator address generation and control module executes the received control instructions, generates corresponding control signals, addresses the back-end LUT ROM, and realizes the DDS signal source. The signals it translates and executes include signal type TYPE_IN, output signal phase DAC2900_Pha, output signal frequency DAC2900_Freq, and output signal amplitude DAC2900_A. The phase accumulator module calculates and generates addresses based on the input signal parameters, which are used to find the amplitude value in the LUT ROM and output the phase. The waveform storage module is divided into sine signals, sawtooth wave signals, square wave signals, and non-periodic Gaussian noise signals generated by periodic signals. Among them: the data stored in sin_rom is a quantized sine wave data of one period. The trig_rom block is not a ROM module, but a triangle wave calculation and generation module. In order to save the RAM module in the FPGA chip, the address is used to generate the amplitude value of the triangle wave in combination with the linear characteristics of the triangle wave, as shown in Figure 7, where K_in[9:0] sets the slope of the generated triangle wave waveform, and clock, address and q[9:0] are compatible with the sin_rom interface. Like trig_rom, square_rom uses a lookup table ROM simulated by Verilog HDL, which can effectively reduce the occupation of FPGA resources. The trig_rom of this design only occupies a 10-bit adder. noise_rom is an improved additive congruential pseudo-random sequence. The design of digital random noise is also the design of pseudo-random sequence, which has good randomness, and its correlation function is close to the correlation function of white noise. Pseudo-random sequence algorithms include: square median algorithm, congruential algorithm, decimal opening method, and Tausworthe sequence. The congruential algorithm includes additive congruential sequence, linear congruential sequence and multiplication and carry algorithm. Combining various algorithms and their implementation complexity and resource reuse rate on FPGA, an improved additive congruential pseudo-random sequence that is easy to implement on FPGA is designed.

Conclusion

Taking into account factors such as cost, performance and application, the logic resources of FPGA are fully utilized to realize a low-end and medium-end measurement system. The dual-channel signal source can work independently to generate undistorted triangle waves, sine waves, square waves and modulated waveforms with a maximum of 2 MHz; the oscilloscope can virtually store a sampling rate of 40 MS/s; the logic analyzer has a maximum sampling frequency of 150 MHz and a storage depth of 256 K×32 bit. It is suitable for teaching experiments. It also cooperates with the host computer software and USB2.0 interface to achieve portability and plug-and-play. The system reserves an Ethernet interface to realize network sharing of measurement equipment. At the same time, it is necessary to further improve the complexity of the system, make full use of the characteristics of FPGA, and dynamically configure the board functions by the host computer.