Research and Implementation of DDS Frequency Modulation Signal Based on FPGA

1 Introduction

Direct digital synthesizer ( DDS ) technology has the advantages of fast frequency switching speed, easy to improve frequency resolution, low hardware requirements, programmable full digitalization, easy monolithic integration, cost reduction, reliability improvement and easy production. At present, major chip manufacturers have successively launched high-performance and multi-functional DDS chips produced by advanced CMOS technology. Special DDS chips use specific processes, with small internal digital signal jitter and high output signal quality. However, in some occasions, since the control method of special DDS chips is fixed, there is a big gap between the working mode and frequency control and the system requirements. At this time, it is a good solution to use high-performance FPGA devices to design DDS circuits that meet your needs. Its reconfigurable structure can easily realize various complex modulation functions and has good practicality and flexibility.

2. Block diagram design of DDS FM signal generator

3. FPGA Circuit Design of DDS Modulation Signal Generator

Figure 2 shows the FPGA circuit design of the core unit of the DDS modulation signal generator. The design adopts the Cyclone series EP1C6T144C6 chip of ALTERA, with a 12-bit adder, a modulation signal waveform memory of 4096×12BIT, a carrier signal waveform memory of 4096×12BIT, and a system clock of 80MHz; design performance parameters: the carrier frequency can reach 10MHz (to ensure that the waveform is not distorted, at least 8 points are taken in one cycle), the modulation frequency range is 0~100K, and the frequency modulation depth is 0~10. The external circuit inputs include the modulation signal frequency control word Kh[11..0], the carrier signal frequency control word Kc[11..0], the frequency deviation control word Kx[11..0], the modulation signal system clock TZCLK, and the carrier signal system clock ZBCLK. Kh[11..0] outputs the accumulated phase ADDA[11..0] as the address of the modulation signal lookup table through accumulator A, and the waveform data Qa[11..0], Kx[11..0] and Kc[11..0] are converted into the frequency modulation control word K[11..0]. K[11..0] outputs the accumulated phase ADDB[11..0] as the address of the frequency modulation signal lookup table through accumulator B, and the waveform data Qb[11..0] is converted by an external DAC and low-pass filtered to obtain the frequency modulation signal waveform. Among them, the DFF buffer connected after the two accumulators helps to eliminate the influence of glitches and further ensure the stability and reliability of the system.

4 Simulation and Experiment

The carrier system time scale frequency is 1MHz, the modulation signal system time scale frequency is 100KHz, the phase accumulator bit is 8 bits, and the address bit and data bit of the two waveform memories are both 8 bits. Use QUERTUS Ⅱ 3.0 to simulate, see Figure 3; use matlab 6.5 to simulate, see Figure 4; use AEDK-EDA experimental box to download (its FPAG chip is EPF10K10TC144-4), D/A conversion and unipolar output circuits are implemented with ispPAC20 chip, and the waveform is observed through Tektronix TDS3054B oscilloscope, the result is shown in Figure 5. The D/A bit number is 8, the measurement range is -4-+4V, and the carrier signal peak value is 1.414V. From the frequency modulation and demodulation waveform data in Figures 4 and 5, the carrier frequency is 14.2kHz, with an error of -3.06%; the modulation frequency deviation is 480Hz, with an error of -1.69%; the modulation index is M=10.21%, with an error of 2.1%, and the modulation frequency is 4.82kHz, with an error of -1.23%. From the experimental results, it can be seen that the design theory and design circuit provided in this paper are not only correct and feasible, but also have good performance parameters. The consistency of all design, simulation and experimental results provides an excellent design solution for the FPGA implementation of the DDS frequency modulation signal generator.

Figure 3 DDS FM wave simulation diagram (QUERTUS II)

Figure 4 DDS FM wave simulation diagram (matlab) Figure 5 DDS FM wave experimental results diagram

5 Conclusion

Using FPGA to implement DDS frequency modulation signal circuit is more flexible than using dedicated DDS chip. As long as the data and control parameters in the ROM in FPGA are changed, DDS can generate any modulation waveform with high resolution and considerable flexibility. In contrast, the function of DDS depends entirely on the design requirements and can be complex or simple. In addition, FPGA chip also supports on-site system upgrade. In addition, embedding DDS design into the system composed of FPGA chip will not increase the system cost much, while the price of purchasing dedicated chip is many times that of the former. Therefore, using FPGA to design DDS system has a high cost performance.