AI inserter power modeling and HBM power noise prediction research

Translated from - Semiwiki, Mike Gianfagna

I attended a session on 2.5D silicon interlayer analysis at DesignCon 2020. As with many of the presentations at this show, ecosystem collaboration was a big focus. In this session, Cadence Principal Application Engineer Jinsong Hu and Enflame Senior Engineer Yongsong He presented methods for interposer power modeling and HBM power noise prediction. Although the focus of the application was on artificial intelligence, the proposed modeling methods have broad applicability.

Enflame Tech is a startup with R&D centers in Shanghai and Beijing. They are developing AI training platform solutions including deep learning accelerators, PCIe boards, and software stacks, targeting cloud service providers and data centers.

Since the focus of this design is AI training, there is a 4-hi HBM2 memory stack on the car to store training data. The ASIC is integrated with HBM2 through silicon intercalation. The ASIC contains a single integrated hard macro physical quantity, which has 8 independent channels, a total DQ width of 1024, and a total number of signals of 3300+.

Two key elements of this project are the design and simulation of the interposer. In terms of signal integrity, the wire length between HBM and PHY is carefully selected because longer lengths require stronger drivers. High-speed signal routing is on M1/M3 and shielding is on M2. All signal routing is designed with a line length difference of ±0.15%. The optimized physical configuration includes signal width, track spacing, and shielding pattern, as shown in the figure below.

AI chips have a large number of HBM dies for parallel calculations, and due to the significant size of micro-bumps and C4 bumps, it brings a certain degree of modeling difficulty to physical design and simulation engineers. For power modeling of the complete interposer design, the Cadence Cadence Sigrity XcitePI extraction tool is used to extract the SPICE netlist model. Model post-processing can verify z-impedance, IR voltage drop, and time domain power ripple, as shown in the following figure.

Power noise is the key to ensure the stability of the HBM bus. At the same time, processing the huge HBM network system signal and power simulation is also a challenge faced by current tools. The report of the design conference proposed two innovative methods to predict HBM power noise, using Cadence Sigrity SystemSI and System Explorer tools for system time domain simulation. Voltage multiplication method and current induction method are used for further power noise prediction. The figure below is a typical scenario. (The acronym "CMF" means "current multiplier".)

Benchmark tests were performed using a test chip mounted on a reference board and showed that the simulation predictions correlated well with the predicted data.

In summary, these power modeling and noise prediction techniques can be widely applied to many different types of 2.5D HBM-based silicon interlayer designs.

Further reading - IR drop

IR drop refers to a phenomenon in which the voltage on the power supply and ground network in an integrated circuit drops or rises. With the evolution of semiconductor technology, the width of metal interconnects is getting narrower, resulting in an increase in its resistance value, so there will be a certain IR drop in the entire chip. The size of the IR drop is determined by the size of the equivalent resistance from the power supply PAD to the calculated logic gate unit.

The current of each logic gate unit in the SoC design will cause different degrees of IR voltage drop to other logic gate units in the design. If the logic gate units connected to the metal wires flip at the same time, the IR voltage drop caused by this will be very large. However, it is very important for some parts of the design to flip at the same time, such as the clock network and the registers it drives. In a synchronous design, they must flip at the same time. Therefore, a certain degree of IR voltage drop is inevitable.  

 IR drop can be local or global. When a certain number of logic gates in adjacent positions have logic flip actions at the same time, it causes a local IR drop phenomenon. When the resistance value of a specific part of the power grid is particularly high, such as R14 far exceeds the expected value, it will also cause a local IR drop. When the logic action in one area of ​​the chip causes IR drop in other areas, it is called a global phenomenon.

IR drop problems often manifest themselves as timing or even signal integrity issues. If the global IR drop of a chip is too high, the logic gates will have functional failures, causing the chip to fail completely, even though logic simulation shows that the design is correct. Local IR drop is more sensitive and can only occur under certain conditions, such as when all bus data is flipped synchronously, so the chip will intermittently exhibit some functional failures. The more common effect of IR drop is that it reduces the speed of the chip. Tests have shown that a 5% IR drop on a logic gate unit will reduce the normal gate speed by 15%.