TSMC prepares to produce HBM4 basic chips: using N12FFC+ and N5 process technology

In response to the needs of the current artificial intelligence (AI) market, it is expected that the new generation of HBM4 storage will have several major changes with current HBM products. The most important of which is the memory stack link interface standard, which will be changed from the already wide 1024-bit , a further shift to doubling to ultra-wide 2048 bits, which makes the HBM4 memory stack link no longer the same as usual, and chip suppliers will need to adopt more advanced packaging methods than now to accommodate the ultra-wide memory of the stack link interface.

At the 2024 European Technology Symposium held recently, TSMC provided some new details about the basic chips that will be manufactured for HBM4. In the future, HBM4 will be produced using a logic process, as TSMC plans to use improved versions of its N12 and N5 processes to accomplish this task. Compared with storage suppliers who currently do not have the ability to economically produce such advanced basic chips, this development is expected to allow TSMC to also occupy a favorable position in HBM4 manufacturing.

According to reports, TSMC is preparing to use two process technologies for the first wave of HBM4 production, including N12FFC+ and N5. According to TSMC’s senior director of design and technology platform, it is working with major HBM storage partners (Micron, Samsung, SK Hynix) to achieve full-stack integration of HBM4 on advanced nodes. Among them, the basic chips produced by N12FFC+ are cost-effective, while the basic chips produced by N5 process technology can provide more basic chips with better power consumption performance under the performance requirements of HBM4.

The report pointed out that TSMC believes that their N12FFC+ process is very suitable for achieving HBM4 performance, allowing storage vendors to build 12-layer stacks (48GB) and 16-layer stacks (64GB), with a bandwidth of more than 2TB/s per stack. In addition, TSMC is also optimizing HBM4 through CoWoS-L and CoWoS-R advanced packaging, reaching more than 2,000 interconnections of HBM4 interfaces to achieve signal integrity .

In addition, HBM4 basic chips produced with N12FFC+ technology will help build system-in-package (SiP) using TSMC's CoWoS-L or CoWoS-R advanced packaging technology, which can provide up to 8 times the reticle size of the interposer, space Enough for up to 12 HBM4 memory stacks. According to TSMC data, HBM4 can currently reach a data transfer rate of 6GT/s at 14mA current.

As for the N5 process, storage manufacturers can also choose to use TSMC's N5 process to produce HBM4 basic chips. The basic chip built on the N5 process will pack more logic, consume less power, and provide higher performance. The most important benefit is that this advanced process technology can achieve very small interconnect pitches, about 6 to 9 microns. This will enable the use of N5 base chips with direct bonding, allowing HBM4 to be 3D stacked on top of logic chips. Direct bonding can achieve higher memory performance, which is expected to be a huge improvement for AI and high-performance computing (HPC) chips that are always seeking greater memory bandwidth.