What? The schematic pins don’t match up again?

Latest update time：2024-06-16

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Reposted from: Linux265

In some new projects developed recently, there are always some big or small problems in the schematic diagrams, either there is no pull-up or the pins are not aligned. Then the embedded software engineers have a terrible time when debugging the single board. Therefore, each step of the R&D process is closely linked. If one link is careless, the entire development cycle will be prolonged. Schematic design is the most basic and core hardware design part of a product, and it must be taken very seriously.

Well, today I happened to see an article about schematic design specifications, as well as some common checklists as experience in avoiding pitfalls. I would like to share them here. As an embedded software engineer, you must have absolute control over schematics. After all, in so many digital products today, embedded software is the brain, and it needs to coordinate the limbs.

1. Confirm the requirements

Understand the design requirements in detail, and sort out the circuit functional modules and performance index requirements from the requirements.

2. Confirm the core CPU

Develop an overall design plan based on functional and performance requirements and select a CPU. The CPU selection has the following requirements:

High cost performance;
Easy to develop: There are many types of hardware debugging tools, many reference designs, rich software resources, and many successful cases;
Good scalability.

3. Reference to successful cases

For the selected CPU chip, choose a successful reference design that is closer to our needs. Generally, CPU manufacturers or their partners will make several development boards for each CPU chip for verification. Although the reference design drawings that manufacturers make public to users are not product-level, they should also be strictly verified. Otherwise, it will affect the promotion and application of their chips. Even if there are some room for improvement in the peripheral circuits they designed, the pin connection and usage methods of the CPU itself are absolutely worthy of our trust. Of course, if there are multiple reference designs with different pin connection methods, you can read the CPU chip manual and errata carefully, or contact the manufacturer for confirmation.

In addition, before designing, it is best for us to borrow or purchase a selected reference board for software verification. If there is no problem, then the hardware reference design can also be trusted. But one thing to note is that many CPUs now have several startup modes. We must choose the most suitable startup mode, or make a compatible design.

Official website information: https://www.nordicsemi.com/Products/nRF51822

4. Selection of peripheral devices

Select components for peripheral function modules according to requirements. The following principles should be followed in component selection:

Universality principle: The selected components should be widely used and verified, and cold-biased chips should be used as little as possible to reduce risks;
Principle of high cost performance: When the functions, performance and utilization rates are similar, try to choose components with better prices to reduce costs;
Principle of convenient purchasing: Try to choose components that are easy to buy and have a short supply cycle;
Principle of sustainable development: Try to choose components that will not be discontinued in the foreseeable future;
Substitutability principle: Try to choose components with a wide range of pin-to-pin compatibility;
Upward compatibility principle: Try to choose components that have been used in previous products;
Resource conservation principle: Try to use all the functions and pins of components.

5. Design peripheral circuits

Modify the peripheral circuit of the selected CPU reference design schematic. When modifying, find at least 3 successful reference designs of the same peripheral chip for each functional module. If the connection methods of the reference designs found are exactly the same, then you can basically rest assured to refer to the design. However, even if only one reference design is different from the others, you cannot simply follow the majority. Instead, you must read the chip data sheet carefully, deeply understand the meaning of those pins, discuss with multiple parties, contact the chip manufacturer for technical support, and finally determine the scientific and correct connection method. If there are still doubts, you can do a compatible design. This is the most critical part of the entire schematic design process. We must do the following:

For each functional module, we should try to find more successful reference designs. The more difficult the design, the more reference designs should be. Successful reference designs are the experience and wealth of "predecessors". We should learn from them and stand on the shoulders of "predecessors", which will improve our starting point.

You should consult and learn from authorities, but you should not blindly trust them, because everyone has cognitive errors, and it is difficult to guarantee that you can always make the most scientific understanding and judgment of even the things you know best. Developers must make the most scientific and correct decisions based on extensive investigation, learning, and discussion;

If you are referring to the design of an existing old product, you should pay attention to the legacy issues of the old product and which functional modules of the hardware are these legacy issues related to. When designing these related modules, you should pay more attention to consideration and cannot mechanically copy the original design.

6. Basic principles of schematic design

Hardware schematic design should also abide by some basic principles, which should be implemented throughout the entire design process. Although these principles are also reflected in successful reference designs, since we may have "pieced together" schematics, we still need to design and review our schematics according to these principles at any time. These principles include:

Digital power supply and analog power supply segmentation;
The digital ground and analog ground are separated and grounded at a single point. The digital ground can be directly connected to the chassis ground (earth), and the chassis must be connected to the earth;
The layout of each functional block should be reasonable, and the entire schematic diagram should be balanced. Avoid some places being too crowded and some places being too loose, the same principle as PCB design;
The corresponding functions of adjustable components (such as potentiometers), switches, etc. must be clearly marked;
Important control or signal lines must indicate their flow direction and functions in words;
Component parameters/values must be accurately marked. Pay special attention to the fact that power resistors must indicate the power value, and high-voltage filter capacitors must indicate the voltage value;
Ensure that the resources of each module of the system do not conflict, for example: the device addresses on the same I2C bus cannot be the same, etc.;
Read the manuals of all chips in the system (usually the design reference manual) to see whether their unused input pins need external processing. If so, they must be processed accordingly, otherwise it may cause internal oscillation of the chip and cause the chip to malfunction.
Try to ensure the convenience of software development without increasing the difficulty of hardware design, or use a small hardware design difficulty in exchange for more convenient, reliable, and efficient software design. This requires hardware designers to understand the underlying software development and debugging, which is a high requirement;
Power consumption issues;
To solve the problem of product heat dissipation, you can add heat sinks or fans to chips that consume more power and generate more heat. The product chassis must also consider this issue. The chassis cannot be made into an insulation box because circuit boards are susceptible to "greenhouses". The product placement location must also be considered. It is best to place it in a location with a larger space and unobstructed air flow to help dissipate heat.

7. Schematic Diagram Review

After the hardware schematic design is completed, the designer should first conduct a self-examination according to the above steps and requirements. After self-examination, he should have more than 95% assurance and confidence before submitting it to others for review. Other reviewers should also strictly review the schematic according to the above requirements. If any problems are found, they should be discussed and analyzed in a timely manner. The analysis and solution process also follows the above principles and steps.

8. Basic requirements for schematic design

As long as the developers and auditors can strictly follow the above requirements for circuit design and review, we have reason to believe that the first version of the circuit board designed by all hardware developers will have a high success rate, so the following points are proposed:

Designers should ensure the correctness and reliability of the schematics. They should ensure that design is auditing and conduct strict self-examination instead of pinning their hopes on the auditors. Designers should be responsible for any problems that arise in the design, and other auditors shall not bear joint liability.
Although other auditors do not bear joint liability, they should also conduct strict review in accordance with the above requirements. Once there is a problem with the design, it also reflects the level, style and attitude of the auditors;
For general schematic design, including the upgrade and modification of old products, in principle, the schematic must be successfully completed in one version, and a maximum of two versions must be completed. Performance penalties will be imposed if more than two versions are completed.
For new designs with complex functions and many doubts, the schematic diagram should be completed within two versions in principle, and closed within three versions at most. Performance penalties will be imposed if more than three versions are completed.
The standard for schematic board sealing is: the circuit board does not have any principle flying wires or other processing points;
Each schematic diagram must have the company's standard drawing frame and indicate the function, file name, name of the drafter/confirmer, date, and version number of the corresponding drawing;
For the relevant analog circuit products that are designed with emphasis, there are no issues with the main chip, peripheral chip, and the connection between chips. Therefore, the selection of components is particularly important, and some basic principles of hardware design must be paid attention to.

9. Schematic design specification checklist

N o.	category	describe
1	Review Rules	The schematic diagram needs to be reviewed, and submission for collective review requires self-inspection to ensure that there are no low-level problems.
2	Review Rules	The schematics are reviewed with the company team and any experts that may be invited.
3	Review Rules	After the first schematic is sent out for collective review, all modifications need to be recorded.
4	Review Rules	The official version of the schematic needs to be reviewed by the manager before it is submitted to the board.
5	Differential Network	In the network of differential lines in the schematic diagram, the P and N at the chip pins should correspond one to one with the P and N of the network command.
6	Single Network	All single networks in the schematic diagram need to be confirmed one by one.
7	Empty Network	All empty networks in the schematic diagram need to be confirmed one by one.
8	grid	1. When drawing the schematic, make sure the grid settings are consistent. 2. There is no situation in the schematic where the network is not connected due to inconsistent grid minimum settings.
9	Network properties	Determine whether the network is a global or local attribute
10	Footprint Library	1. The device package in the schematic diagram is consistent with the manual. 2. Whether the device in the schematic diagram is a symbol of the standard library.
11	Drawing requirements	The device packaging in the schematic is consistent with the manual.
12	Indicator Lights	The design defaults to an indicator light that is lit by the power supply and an indicator light that is turned off by the MCU, which makes it easy to intuitively determine whether the problem is the power supply or the MCU.
13	Network port connector	Confirm the opening direction of the network port connector, whether it has an indicator light, and whether it has PoE
14	Network port transformer	Confirm whether the transformer selection meets the requirements, such as with PoE
15	button	Confirm whether the button model is a straight button or a side button
16	Resistor pull-up and pull-down	Avoid repeated pull-up or pull-down on the same network
17	OD Gate	The output pin of the chip's OD gate or OC gate needs to be pulled up
18	match	The beginning and end of the high-speed signal need to reserve series resistance
19	triode	The transistor circuit needs to consider the current carrying capacity
20	Testability	Add ground holes near key circuits and chips on the board to facilitate testing
21	Connector foolproofing	When selecting a connector, you need to choose a model with a fool-proof design
22	simulation	Low-speed clock signal, the driving capability, matching method, and interface timing of the device connected to the bus interface must be confirmed by simulation, such as MDC/MDIO, IIC, PCI, Local bus
23	simulation	The circuit uses inductors and capacitors with appropriate Q values, which can be simulated.
24	Timing	Confirm whether the power-on sequence meets the chip manual and recommended circuit requirements.
25	Timing	Confirm whether the power-off timing meets the chip manual and recommended circuit requirements.
26	Timing	Confirm whether the reset timing meets the chip manual and recommended circuit requirements.
27	Reset switch	The design of single-board key switches should prevent the single-board from hanging due to long-pressing the key. It is recommended that the key switch be designed to only generate a short pulse width low level.
28	Reset Design	Reset signal design (1) Pull up and down according to chip requirements (2) Confirm the default state of chip reset (3) Peset signal is connected in parallel with a capacitor of tens of PF to filter and optimize signal quality. (4) Reset signal ensures model integrity.
29	Reset	All interfaces and optical modules are in reset state by default.
30	Level Matching	Interconnection of different level standards, focusing on voltage, input and output thresholds, and matching methods.
31	Power consumption	Review the power consumption design of each chip in detail, calculate the maximum power consumption of each voltage of the board, and select a power supply with a certain margin.
32	Slow Start	Hot-swap circuits require slow start design
33	Magnetic beads	The ferrite beads at the output port of the power supply with small voltage and large current (ampere level) need to consider the ferrite bead voltage drop
34	Connector	The current capacity and voltage drop of the power connector between boards are reserved
35	Logo	Check whether the network identification of the daughterboard and motherboard sockets are consistent, and the pin signals of the front and rear cards connected to the machine must correspond one to one.
36	Level Matching	For one-drive multiple signals, impedance matching should be performed based on simulation results to determine whether to add matching resistors at the beginning or end.
37	Matching level	When designing schematics, you should pay attention to the manufacturer's device information, and there will be clear matching requirements for inputs and outputs.
38	Diode	When using diodes in control, detection, power-on and other circuits, it is necessary to consider whether the reverse leakage current of the diode meets the design requirements.
39	not	Unused input/output pins of CMOS devices must be processed according to the device manual. If the manual does not require it, the processing method must be confirmed with the manufacturer.
40	Warmth	The temperature of key components should be monitored
41	244/245	Signals that require pull-up or pull-down need to have pull-down added to the input and output ends of the bus driver after passing through a bus driver without an output hold function.
42	244/245	If 244/245 does not have a hold function, the unused input pins must be pulled up or down.
43	clock	The signal directly output by the crystal oscillator pin cannot be directly driven by one load. Multiple loads will affect the signal quality. It is recommended to use a one-to-one method.
44	clock	A 0402 series resistor is required to connect the crystal's XT-out to the clock driver, and the resistance value should not affect the board's vibration.
45	clock	The selection of phase-locked loop circuit and parameters must be subject to special calculations.
46	clock	The clock loop filter ceramic capacitor is preferably an NPO dielectric capacitor.
47	clock	Confirm whether the signal swing, jitter, etc. exceed the device requirements.
48	clock	Confirm that the clock device can fully meet the requirements in terms of center frequency, operating voltage, output level, duty cycle, phase and other indicators.
49	DDR	DDR and other memory interfaces must have clock frequency derating design.
50	DDR	For boards with higher reliability requirements, it is recommended to meet ECC design rule requirements during RAM development.
51	DDR	The VTT power supply filtering of DDR requires the combination of Vtt resistor and green capacitor.
52	PHY	MDC/MDIO adopts a one-drive-many matching method. The master device is connected to the slave device through a series resistor -> pull-up resistor -> series resistor. The series resistor should be placed at both ends.
53	PHY	For one-to-many control, PHY needs to reserve address signals for control.
54	PHY	The power consumption of chips such as CAM varies greatly depending on access conditions and temperature. When designing, you must carefully consult the device manual to clarify the relationship between power consumption and the manufacturer's chip.
55	PHY	If the device has an optical module interface, a 10nf capacitor is connected in series inside the optical module, and the link does not need to be redesigned.
56	heat sink	When choosing a radiator, consider the weight of the radiator and how it will fit into the device.
57	I2C	When devices are interconnected via I2C, they can use the I2C module on the chip or through the I2C module.
58	capacitance	When designing the RF-related parts of the board, bypass and filter capacitors are required. Filter capacitors with different capacitance values should be selected for different interference frequencies.
59	capacitance	When designing capacitors in parallel, the resonance point must be calculated or analyzed through simulation to avoid possible resonance problems.
60	capacitance	When designing the filter capacitor, attention should be paid to the impact on the control pin.
61	capacitance	How to use the unused pins requires referring to the chip manual and the design of the demo board to pay attention to whether the design of these pins is reasonable.
62	Characteristic impedance	When there are special requirements for the characteristic impedance of PCB routing, special instructions need to be given in the schematic diagram or in the requirements document for the interconnect engineer.
63	Reset Design	Independent reset designs should be reserved for key functional devices.
64	Reset Design	Many Flash memories have an RST pin. To meet the requirements of software function implementation in the startup phase,
65	RF Filtering	When designing the power supply of the video amplifier, it is necessary to add appropriate filter capacitors to prevent power supply noise from having a negative impact on the quality of the RF signal.
66	RF Filtering	Power supply and power circuit design are the selection of application circuits that need to consider the power characteristics of resistors.
67	Testability	Some functional modules should remain in a long-term working state to facilitate hardware testing.
68	RF Circuit	Whether the DC bias circuit needs to be enabled and whether the control voltage accuracy meets the requirements of the amplifier.
69	RF Circuit	Ensure that the maximum RF peak power that can be output by the front stage is about 3dB less than the maximum limit input power of the subsequent cascade device. Pay attention to the impact of signal peak and overshoot on device overpower.
70	RF Circuit	The center heat sink pad of the RF device power amplifier must be grounded on the schematic diagram.
71	RF Circuit	The RF device has on/off function. In the off state, there is a problem with isolation. The isolation affects the interference of transmission and reception. The interference signal needs to be kept within a reasonable level, otherwise it will affect the normal operation of the chip set.
72	RF Circuit	The positive and negative feedback design of the PA peripheral circuit in the RF transmitting end link of the PA prevents the PA from burning.
73	RF Circuit	For the RF receiving circuit, a PI-type position needs to be reserved between the receiver and the chip set to debug the receiving sensitivity.
74	power supply	Ensure that all power conversion modules OCP/OVP points (overcurrent protection point and overvoltage protection point) are set correctly
75	power supply	电源的带负载能力是否足够，相数是否足够，能提供足够大的电流、功率給CPU,Chipset等（1相按最大20A计算，保守15A）
76	power supply	The frequency range of PWM single-phase is 200K-600K; the integrated MOS can reach 1MHz
77	power supply	Input capacitor ripple current (reference 2700mA); small capacitor ripple current will cause the capacitor to heat up and shorten its life
78	power supply	Is the ESR of the output capacitor small enough?
79	power supply	Whether the withstand voltage of the capacitor is met and the derating is met
80	power supply	H-MOS has a short conduction time; L-MOS has a long conduction time
81	power supply	H-Side MOSFET should be selected with fast conduction speed
82	power supply	L-Side MOSFET should be selected with low Rds(on)
83	power supply	The power loss of a linear power supply is P=Δvi. Generally, the power loss that an LDO can withstand is PmaxJunction=device Temp, ensuring that the sum of device temp and ambient temp is less than 80% of the maximum operating temperature of the MOS.
84	power supply	The names of the same power supply and ground on a single board should be unified
85	power supply	Connect a 0.1uF capacitor between the BOOT Pin and the Phase terminal of the single-phase PWM driver. Check whether the BOOT capacitor has a withstand voltage of 50V. After the H-MOS is turned on, the BOOT Pin voltage reaches 24V and the Phase terminal 12V.
86	power supply	A 0ohm resistor is reserved on the H-side Gate to prevent the High-side MOS from being broken down due to excessive Vgs.
87	power supply	Check whether the feedback circuit setting is accurate; annotate the feedback voltage calculation formula on the circuit.
88	power supply	The GND and AGND circuits should be separated, but they should be connected at one point. If the AGND current of the chipset is large, it can be directly connected to GND without connecting 0OHM, otherwise the current will not be enough.
89	power supply	The pull-up of PWROK needs to be pulled up with the corresponding power supply.
90	power supply	After copying some module lines, you need to pay attention to changing the AGND attributes. It is best to give a net name. For example, it is often encountered that the AGND of two P1V1s have the same name.
91	power supply	Confirm the inductor package and check whether the saturation current meets the circuit requirements. The larger the inductor package, the stronger the overcurrent capability, and the saturation current of the inductor should be greater than the OCP current of the circuit.
92	power supply	Confirm the compensation circuit to ensure sufficient crossover frequency and phase margin.
93	power supply	Check whether the maximum voltage drop of the LDO meets the device requirements (input voltage range and output voltage range)
94	FPGA	Confirm whether the logic level of input and output is correct; level type: GTL, OD, LVCMOS33, LVCOM25, LVDS, etc. Confirm whether the logic level between the chip and CPLD/FPGA matches to avoid inconsistent levels on both sides.
95	FPGA	When the GPIO signal of CPLD is used as an output pin to control the timing, this pin needs to be pulled down through a 4.7K to 10K resistor.
96	FPGA	The JTAG interface of the CPLD needs to be connected to the Header. Note that the pin definition of the Header meets the requirements of the programmer and an ESD protection circuit is reserved for the JTAG signal.
97	FPGA	The spare unused GPIO Pins are connected to LEDs, usually 3-4 LEDs are enough.
98	FPGA	For GPIO with the same function, try to use only the same Pin (except Reset signal)
99	FPGA	The voltage levels of different banks are related to the VCCIO level of this bank.
100	FPGA	When connecting an external ROM to the FPGA, the order of 1, 2, and 3 must be marked in the schematic diagram (wrong order will result in failure to program). Ensure that the interface level between signal connections is correct and whether levelshift design is required.
101	FPGA	The timing of CPLD core power and IO power generally requires that the core power should be earlier than the IO power, otherwise, the output signal needs to add a pull-down resistor. (Generally, the core power is earlier than the IO voltage, and the IO state can be fixed after the core is up. For specific requirements, refer to the manufacturer's device data)
102	FPGA	If the MGT Bank of the FPGA is not in use, the RX signal needs to be grounded.
103	FPGA	MGT Bank refers to a bank that can be configured as a high-speed interface, such as Xilinx's GTP and GTX interface banks. When not in use, the RX signal needs to be processed.
104	FPGA	During the schematic design period, the CPLD programmer must be provided with a standardized CPLD requirements document.
105	FPGA	The input and output states of each pin must be specified in the CPLD requirements file.
106	FPGA	For CPLD, use as little sequential logic as possible, use more combinational logic, and replace complex logic with simple logic as much as possible.
107	FPGA	The logic requirements provided by the designer should avoid competition and risk, that is, use the CPLD output signal as the input judgment of other logic
108	FPGA	If there is a design requirement to support I2C, the system I2C topology should be planned in advance, and the reserved logic space should be considered when selecting chips. (If the BMC has sufficient I2C resources, the CPLD will occupy a set of I2C buses separately)
109	Connector	The bandwidth of the high-speed connector should be selected according to 1.5-2 times
110	Connector	Confirm the Pin definition of the connector on the PCB
111	Connector	Whether the corresponding pin signal definitions of the two plug-in board connectors are consistent. For the interconnection of multiple boards, it is necessary to confirm whether the physical position of the corresponding connector is correct.
112	Connector	Determine whether welding and crimping devices can be used based on the thickness of the board
113	Connector	Generally, the female end of the connector should have long and short pins, so the female end needs to define power and GND
114	Connector	High-speed signal connector, the GND Pin around the high-speed signal must be grounded
115	Connector	When defining high-speed signal connectors, pay attention to the distribution of TX and RX on the connector to avoid mixing TX/RX (to avoid cross talk)
116	Connector	As an interface composed of two connectors, you need to choose connectors of the same manufacturer and type.
117	Connector	When selecting SMD connectors, there should be a flat surface on them to facilitate the high-speed machine nozzle to pick them up and prevent them from falling off. For packing, disk packaging is preferred instead of tubular packaging.
118	Connector	Try to unify them into welding devices or crimping devices
119	Connector	Pay attention to the choice of pin length
120	Connector	Before entering the layout, be sure to provide a sequence diagram of the connector positions.
121	Connector	When selecting connectors, try to choose common materials (from more than two sources) to ensure a certain degree of substitutability.
122	Connector	When selecting a connector, the thickness-to-diameter ratio of the PCB needs to be considered (not to exceed 10:1)
123	Connector	When choosing an Ethernet port connector, pay attention to the color of the connector, as different colors will affect the appearance of the product.
124	Connector	Interfaces of different rates and types, such as 10GE, GE, FE, control, and debug ports, can be distinguished by mask colors.
125	Connector	When selecting a connector, you need to pay attention to whether it has positioning pins. If it does not have positioning pins, it may be misaligned during production and processing.
126	Connector	When selecting a connector, you need to pay attention to the relationship between the pin length and the PCB thickness. If the pin is too long, it needs to be shortened when the single board is produced and processed. If the pin is too short (such as the positioning pin), it will appear warped during the single board processing.
127	clock	For clock signal (except differential signal), a capacitor position for adjusting EMI should be reserved, usually 10pF.
128	clock	It is recommended that the clock signal of the PCI-E2.0 slot be from the same source as the controller chip.
129	clock	When Clockgen or Clock Buffer uses SYS power supply, please pay attention to whether the clock signals of chips such as network cards and CPLDs require separate clock sources.
130	clock	The pull-up voltage of the SMbus interface of all Clockgen and Clock Buffer should be consistent with the power supply of the IC
131	clock	When the output level of the crystal oscillator or clock buffer is inconsistent with the level required by the IC, AC coupling and impedance matching circuits need to be added. At the same time, attention should be paid to whether the SWING and CROSSPOINT settings are correct.
132	clock	Pay attention to the output level of the Ossilater clock signal. If it is LVPECL, a 150 ohm resistor to ground needs to be added externally. For emitter-coupled logic circuits, a ground return path needs to be provided on the periphery.
133	clock	The CPU crystal oscillator should be arranged as close to the crystal input pin as possible. A passive crystal oscillator needs to add a capacitor of several tens of picofarads; an active crystal oscillator can directly lead the signal to the crystal input pin of the CPU.

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