Power management and power consumption allocation of intelligent driving systems

When designing the architecture of a high-end autonomous driving system, the internal architecture of the domain control usually involves the main control chip MCU, computing chip SOC, power management module chip PMIC, deserializer, CAN transceiver, network switch, etc. These design elements mentioned are not just a simple hardware connection and wiring to a certain extent from the bottom level, but from a software perspective, the network configuration, power management, storage configuration, etc. of the related systems involved need to be corresponding simultaneously. Development of software and hardware modules. Among them, power configuration and network startup configuration, as two relatively important high-end domain control configuration units, have always been part of the design content that system architects, hardware architects, and software architects need to overcome.

This article will take a typical system architecture formed by a power management chip PMIC that is popular in the industry as an example to provide detailed power management instructions and network management instructions for the power management solution. This includes the power distribution network (PDN) between the two power management module PMICs (typical of the TPS6594-Q1 device) and the DRA829V with independent MCU and main power rails (TI's DRA829V is a dual Arm® Cortex®-A72, Quad-core Cortex®-R5F, 8-port Ethernet and 4-port PCIe switch.) or TDA4VM (Smart Driving Domain Control SOC Processor).

The TDA4 series chip can be used as a classic low-level version of a hyper-heterogeneous chip. Its corresponding internal processor can be used as an independent security monitor (MCU security island) resource for main processing, which is needed to ensure the safe operation of the system. MCU processors need to maintain minimal system manipulation capabilities (also known as MCU Only mode) to significantly reduce processor power consumption, thereby extending battery life during standby use cases and reducing component temperatures.

Power management profiles of different intelligent driving system architectures

Of course, the degree of use and scenarios of intelligent driving system chips in the industry vary according to their application requirements. As an entry-level version of a hyper-heterogeneous chip, generally speaking, the L2 level requires 5 TOPS of computing power, the L3 level requires 100+ TOPS of computing power, and the L4 level requires 300+ TOPS. Therefore, low-level driving assistance systems (L0~L2) usually use a single chip such as TDA4VM (8Tops+25KDMIPs) to meet the overall demand for computing power. The processing capabilities of chips such as sub-high-end (L2+~L4) have become somewhat inadequate. Considering that the current focus of research and development in the entire industry tends to be systems such as L2+. Therefore, the power distribution management solution introduced in this article mainly considers the situation of multiple SOCs, such as typical TDA4 VH, 8650, etc. as examples to illustrate the architecture.

The figure below shows the difference in power control logic between pure heterogeneous chip architecture and ultra-heterogeneous chips.

In terms of domain control architecture design, hyper-heterogeneous chips often concentrate all computing resources on one chip, and this chip basically handles all related chips (such as deserializers) in the smart driving domain control. , switch, Can transceiver, camera control terminal) for driving and power supply control. Therefore, we usually call this type of control connection serial control, that is, the control link of the power supply is usually managed by a unified PMIC to the central chip. Of course, if the low-power consumption characteristics of the architecture are taken into account, it is possible to split the PMIC of the control central chip into master and slave channels for separate control. The main circuit realizes power control management under full power consumption. The secondary path is to implement independent power management when the user needs to reduce power consumption (for example, only activate the internal MCU Only module through the PMIC link setting).

For pure heterogeneous chip intelligent driving domain control architecture, when designing the power tree, the single-chip single-control method is usually used. For example, if three types of chips, MCU, SOC, and GPU, are considered to be integrated into the same system architecture, , then the separated power supply control method is usually adopted, that is, the power supply of each chip is independently controlled on and off. The power on and off control of chips such as deserializers and CAN transceivers is equipped with separate power control modules based on user customized needs. For example, consider power control for wake-up CAN alone, or power control for bypass image output control alone. Chips such as Switch can be controlled on and off through the MCU alone.

Intelligent driving system basic power tree design

The figure below shows the power tree structure of the intelligent driving system that will be introduced in detail in this article. The entire front-end power supply of the power tree is provided by the vehicle power battery. Considering the huge power consumption of the intelligent driving system, usually the power supply is a high-voltage large battery power supply mode. Of course, in some special circumstances, it can also be switched to small battery power supply (such as the sentry mode that is activated within a certain period of time after power off, or the long endurance mode that is activated in the later stages of driving of new energy vehicles). In addition, for power wake-up, there are also different wake-up methods (ACC file is directly powered on and ignited through IG ON, CAN network wake-up message injection, or other mechanisms that consider the need to independently start the chip wake-up work).

The initial DCDC step-down conversion involved in the entire power-on management process is generally to convert the 12V battery power supply into a lower voltage according to the demand, such as 5V, 3.3V and other voltage values ​​for use by different chips. For example, TDA4 requires 3.3V power supply, and other chips require 5V voltage power supply. Then, only after the initial voltage transformation is connected to the PMIC power management module, the main computing chip of the intelligent driving system can be directly powered through voltage distribution control. Of course, there are also some chips (such as deserializer 1.0V-1.8V, CAN transceiver 5V, Ethernet Switch 1.0V-3.3V, etc.) that require secondary voltage transformation according to their own needs after the initial voltage reduction configuration Post DCDC . In addition, there will be mutual dependence between the startup of the intelligent driving system and data processing. Usually, depending on the data source it processes, the central computing chip SOC/MCU will be considered as the control enabler for other chips. For example, if the SOC is used for data processing of visual perception input sources, then a control connection line (such as an IIC line) needs to be set between the SOC and the deserializer and the Power Switch that directly supplies power to the directly connected camera as an enabler. line adjustment. In addition, if the MCU is used as a data processing terminal for millimeter wave radar (trajectory planning), it controls the central task of inputting and processing millimeter wave radar data. The corresponding CAN transceiver enablement and power control can be controlled by the smart driving domain control. The MCU can be used for direct control and can also be directly connected to the vehicle's normal power supply.

The entire power tree design process requires reverse voltage design, wake-up response design WakeUp, voltage stabilization design/voltage transformation design (DCDC, LDO, PMIC), power switch design Power Switch, etc. The following lists several typical chip selections and corresponding characteristic parameter descriptions.

1) LDO (MPQ20051): Low dropout linear regulator that can provide up to 1A current and 140mV voltage. When the input voltage is 2.5V to 5.5V, its corresponding adjusted output voltage range is from 0.8V to 5V. The internal PMOS pass element allows a low ground current of 130uA, making the MPQ20051 suitable for battery-powered equipment. Other features include low-power shutdown, short-circuit and thermal protection.

2) DCDC (MAX20074ATBA/V+): represents a buck switching regulator IC. The lowest automotive synchronous buck controller using only 3.5µA quiescent current at light loads.

3) DCDC (MPQ2166): is an internally compensated, dual, PWM, synchronous, buck regulator that operates from an input voltage of 2.7V to 6V and produces an output voltage as low as 0.6V. The MPQ2166 can be configured as a 2A/2A or 3A/1A output current regulator with quiescent current as low as 60µA. The MPQ2166 features peak current mode control, internal compensation, and is capable of low dropout configuration. Both channels can operate at 100% duty cycle, with full protection features including cycle-by-cycle current limiting and thermal shutdown.

4) PowerSwitch (MAX20086–MAX20089): Dual/quad camera power protector IC provides up to 600mA load current for each of its four output channels.

As for PMIC chips, the following are mainly used here to achieve different power management controls.

5) PMIC (PF71): This is a power management integrated circuit designed for the high-performance i.MX 8 processor. It features five high-efficiency buck converters and two linear regulators to power the processor, memory, and other peripherals. Built-in one-time programmable memory stores critical startup configurations, greatly reducing the number of external components typically used to set the output voltage and external regulator sequencing. Regulator parameters can be adjusted after startup via high-speed I2C, providing flexibility for different system states.

6) PMIC (TPS6594-Q1): As a power management chip IC, TPS6594-Q1 has 5 BUCKs and 4 LDOs. It is especially suitable for automotive applications related to smart driving safety in the industry. The device provides four flexible multiphase configurable BUCK regulators with 3.5A output single-phase current, and an additional BUCK regulator with 2A output current. Each output is individually protected against short-to-battery, short-to-ground, and overcurrent conditions. These ICs operate from 3V to 5.5V supplies and 3V to 15V camera supplies, with an input-to-output voltage drop of only 110mV (typ) at 300mA.

7) Primary DCDC (MAX20098): Automotive 2.2MHz synchronous buck controller IC with 3.5µA IQ. The IC operates from an input voltage of 3.5V to 42V and can operate at 99% duty cycle in dropout conditions. This approach is suitable for applications with medium to high power requirements that operate over a wide input voltage range, such as providing the necessary voltage during automotive cold start or engine stop-start conditions. The IC also provides an output of the time synchronization signal SYNC, enabling the two controllers to operate in parallel. FSYNC input programmability supports three frequency modes to optimize performance: forced fixed-frequency operation, jump mode with ultra-low quiescent current, and synchronization to an external clock. This IC can minimize EMI interference when used with programmable spread spectrum options for frequency modulation.

Instance-based power network management

This article details how dual PMIC (TPS6594-Q1) power supplies are connected to typical processors and other peripheral component use cases to effectively support Power Distribution Network (PDN). The power network management module PDN can realize board-level isolation of the main microprocessor core MCU and other high-computing power chip voltage resources according to the power requirements of its processor. At the same time, this board-level power isolation is used to achieve the ideal product functional architecture.

The design of the entire power distribution network PDN mainly includes the following contents:

① PDN power connection

② PDN digital control connection

③ The default internal modules of the primary and secondary PMICs manage NVM content

④ PMIC sequencing settings to support different PDN power state transitions of advanced processors

System PMIC data processing needs to describe recommended operation, electrical characteristics, external components, packaging details, register mapping and overall component functionality. PMIC (TPS6594-Q1) devices are available in different orderable part numbers (PN) with unique NVM settings to support different end product use cases and processor types. Each PMIC's unique NVM setup device is optimized for each PDN design to support different processors, processing loads, SDRAM types, system functional safety levels and end product features such as low power modes, processor voltages and memory subsystem). NVM settings can be identified by the module ID number NVM_ID and the module register NVM_REV. Each PMIC device can be distinguished by the part number, NVM_ID and NVM_REV value.

The figure below shows the power mapping between the PMIC power management of the dual TPS6594-Q1 and the processor. This connection supports the voltage domains required by the independent MCU and the main power rail.

As shown in the figure above, the PDN requires an external power FET in series between the input supply and the PMIC. The PMIC implements voltage monitoring before and after the FET through the OVPGDRV pin. When an overvoltage event greater than 6 V is detected, the FET can quickly isolate the PMIC on the input power supply to protect the system from damage. This includes all power rail FET output signals from any power supply connected upstream of the FET and is not protected from overvoltage events. The load switches that power the MCU and main I/O domains, the discrete buck power supply DDR, and the discrete regulator LDO that powers EFUSE are all connected behind the FETs, which prolongs the process life of these processor domains and discrete power supplies. Voltage protection capability.

In addition, the internal structure of the entire power management module as shown in the figure above also includes the following corresponding parameter settings.

In the above configuration, both PMICs use a 3.3 V input voltage. For functional safety applications, there is a protection FET connected to the OVPGDRV pin of the main PMIC before VCCA, allowing the input supply voltage of the PMIC to be monitored. The VCCA voltage must be the first voltage applied to the PMIC device. The VIO_IN of the PMIC supplies power to the VIO_IN in the corresponding PDN through the load switch after VCCA. The load switch also provides the voltage source for the VDDSHVx_MCU processor. By introducing the PMIC GPIO control signal of VIO_IN, it can ensure that it can remain active during the MCU Only low power mode and do data saving in DDR (also called suspend to RAM). ) period is disabled to reduce PMIC power consumption.

For dual-voltage I/O situations, it needs to support both 3.3V and 1.8V situations. Using a processing-side LDO with a logic high default value sets the initial voltage I/O value to 3.3 V via the GPIO control signal. During processor power-up, the bootloader SW can set the GPIO signal low, ensuring that the consumer selects the appropriate level (1.8 V) as needed. At the same time, when the MCU is not started, the PMIC can control the LDO1 voltage processor to establish I2C communication with the PMIC during the operating system startup.

Here we can give an example of how to implement MCU Only control logic on some ultra-heterogeneous chips. For example, in the MCU Only mode control of the TDA4 chip, four discrete power components need to be used in the power distribution network PDN, three of which are required and one is optional, depending on the characteristics of the final product. Two TPS22965-Q1 load switches connect the VCCA_3V3 power rail to the power protection processor I/O domain. Usually two load switches are needed to isolate the computing domain NPU and real-time domain MCU, and control each module individually. Of course, power isolation can also be established between the main processor for MCU Only low-power operation. The TPS62813-Q1 buck converter also provides the required supply voltage (1.1V) to the memory cell LPDDR4 SDRAM component.

Additional connecting GPIO lines from the TPS6594-Q1 device to the processor can also be signaled to provide error monitoring, processor reset, processor wake-up, and system low-power modes. Specific GPIO pins need to be assigned to specific key signals, which ensures normal operation in low-power mode when there are only a few GPIO pins.