How many 32-bit RISC processors can be integrated into an FPGA today?

By: Steve Leibson, Director of Strategic Marketing and Business Planning, Xilinx

Jan Gray is an expert in integrating 32 -bit RISC processors in FPGAs . He writes a blog called FPGA CPU News , subtitled " Developing Parallel Computer Architectures with FPGAs ". Jan Gray 's latest post is FPGAs, Then and Now , which compares the integration of the J32 32-bit RISC CPU in a Xilinx XC4010PC84-5 FPGA in 1995 with the integration of the same processor in a current Xilinx Virtex-7 XC7VX690T FPGA . The J32 processor Gray uses uses a classic RISC architecture with 3-operand instructions, a 4=stage pipeline (fetch, register read, execute, write back), and a 32 -bit operand register file.

In 1995, Gray used a J32 processor that essentially consumed 800 4-input LUTs in an XC4010 FPGA . The processor arrangement looked like this:

13 years later. The same J32 processor core is integrated into a Virtex-7 FPGA , which supports more than 433,000 6 - input LUTs , 1000 times the space reserved for 250 router cores and 1000 processor interconnects . The arrangement of the J32 RISC processor looks like this:

"That is to say, in the past 18 years , Moore's Law has upgraded each FPGA from 1K LUTs to 1K 32-bit CPUs . (By the way, the largest Virtex Ultrascale 3D FPGA has 4.4 million logic cells, so the logic capacity is enough to interconnect more than 10,000 of the 32- bit RISC J32 CPUs mentioned by Jan Gray . See the note below !)

If your system design involves processor and FPGA interaction, check out Jan Gray 's blog post at FPGA CPU News .

Note: Jan Gray points out that the Virtex UltraScale VU440 FPGA has 2,520 BRAMs , so there are limitations to implementing direct ports in Gray's design, which can only be used for 2,520 32-bit RISC processor cores. Perhaps the Virtex UltraScale XCVU160 with more BRAMS and less logic resources is a better choice. I will explain this in detail in a future article.