HLS Tutorial Video 4: HLS Design Process - Example Demonstration
This series of instructional videos is led by Xilinx senior strategic application engineers to guide you from scratch and step by step to master HLS and UltraFAST design methods, helping you become an expert in system design and algorithm acceleration!
Course update time: the second and fourth Tuesday of each month
In the previous course, we introduced the introduction to HLS and explained the working principle of HLS through examples. This course will demonstrate the Vivado HLS design process through specific examples, including design input, C simulation, C synthesis, and C/RTL co-simulation.
Xilinx senior strategic application engineer . Focused on C/C++ high-level synthesis, with many years of experience in implementing digital signal processing algorithms using Xilinx FPGA, and has a deep understanding of Xilinx FPGA architecture, development tools and design concepts. Released the online video course "Vivado Getting Started and Improved" with more than 50,000 hits, and published the book "FPGA-based Digital Signal Processing (2nd Edition)", which was widely praised.
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