Here's the origin | Breaking out of the LLC series resonant converter mindset

For more than a decade, the power industry has widely adopted the inductor-inductor-capacitor (LLC) series resonant converter (LLC-SRC) shown in Figure 1 as a low-cost , high-efficiency isolated power stage. It contains two resonant inductors (two "L": Lm _and Lr ₎ and one resonant capacitor (one "C": Cr ₎ . LLC-SRC devices have soft switching characteristics and do not have complex control schemes. Due to the soft switching characteristics, the device supports the use of components with lower voltage ratings and improves efficiency. The device uses a simple control scheme, namely a variable frequency modulation scheme with a fixed duty cycle of 50%, which requires a lower cost controller than the controller used for other soft switching topologies such as the phase-shifted full-bridge converter.

Figure 1. LLC-SRC

Although LLC-SRC can be much more efficient than hard-switched flyback and forward converters, there are still some design challenges to achieve the best efficiency.

First, in LLC-SRC design, to achieve a wide enough controllable range, the ratio of the two resonant inductors (Lm _/ Lr ₎ may have to be less than 10. At the same time, Lm needs to _have a large inductance to reduce circulating current, so Lr inductance needs to be kept high _to ensure the resonant inductance ratio is low.

It is important to note that the current in the series resonant inductor Lr _{is purely AC without any DC component, which means that the flux density variation is large (i.e., ΔB is high).} High ΔB means that the AC-related inductor losses are also high. If the inductor is wound on a ferrite core, the edge effects near the core air gap will produce high winding losses.

_A high Lr inductance means more inductor turns and higher AC winding losses. Therefore, many LLC-SRC designs use powdered iron cores for the resonant inductor, making a trade-off between winding losses and core losses. However, a high ΔB results in considerable losses on the resonant inductor: either high winding losses or high core losses.

The second challenge of LLC-SRC design is how to properly optimize synchronous rectifier (SR) control. LLC-SRC rectifier current conduction timing depends on load conditions and switching frequency. The most promising LLC-SRC SR control method is to detect the SR field effect transistor (FET) drain-source voltage (VDS) and turn the SR on and off when VDS is below or above a specific level. VDS detection methods require millivolt-level accuracy and can only be implemented in integrated circuits. Self-driven or other low-cost SR control schemes are not suitable for LLC-SRC because such devices use current-fed output configurations with capacitive loads. Therefore, the cost of LLC-SRC SR controller circuits is usually higher than that of other topologies.

To address these two challenges (high inductor losses and SR control) while maintaining most of the benefits that a resonant converter can offer, consider using a modified CLL multi-resonant converter (CLL-MRC), as shown in Figure 2.

Figure 2. Improved CLL-MRC

Unlike the CLL-MRC where all three resonant elements (one capacitor and two inductors) are on the input side, the modified CLL-MRC moves one inductor from the input side to the output side and places the inductor after the rectifier L _o , as shown in Figure 2. This modification allows a DC current to flow through the resonant inductor, which means smaller ΔB and potentially lower magnetic losses.

Figure 3 shows the operation of the modified CLL-MRC, where f _sw is the converter switching frequency and f _r1 = {2π[C _r (L _r1 //L _r2 )] ^0.5 } ^-1 is one of the two resonant frequencies. When f _sw is lower than f _r1 , the output winding current drops to zero before the end of the switching cycle, similar to the output winding current in LLC-SRC. Now, there is an inductor at the output. A simple set of capacitors and resistors can sense the output inductor voltage. Every time a large rate of voltage change (dV/dt) occurs, it is time to turn the SR on or off. Therefore, the SR control scheme is less expensive than the V _DS sensing scheme.

When f _sw is higher than f _r1 , the output inductor current will be in continuous conduction mode. In other words, compared with LLC-SRC, ΔB is reduced, the inductor AC loss can be greatly reduced, and the converter efficiency can be improved.

Figure 3. Important waveforms of the improved CLL-MRC:

f _sw < f _r1 (left), f _sw > f _r1 (right)

To verify these performance assumptions, I built an LLC-SRC and another modified CLL-MRC power stage with exactly the same components and parameters. The only difference between the two is that a 72μH inductor is used as the LLC-SRC resonant inductor and a 1μH inductor is used as the modified CLL-MRC output inductor.

Figure 4 shows the efficiency measurement results of the two power stages. When the input voltage is low, f _sw is smaller than f _{r1 , so the L o} current in the modified CLL-MRC is still in discontinuous conduction mode with a large ΔB. Therefore, the modified CLL-MRC has no efficiency advantage under this operating condition.

When the input voltage increases, f _sw is greater than f _r1 and the L _o current is in continuous conduction mode. With a 430V input, the efficiency of the modified CLL-MRC is 1% higher than that of the LLC-SRC. This comparison shows that if the modified CLL-MRC is designed to always operate at a frequency higher than f _r1 , its efficiency performance over the entire range may be better than that of the LLC-SRC.

Figure 4. Converter efficiency at different input voltage levels:

Improved CLL-MRC (top), LLC-SRC (bottom)

The LLC-SRC is indeed an excellent topology that offers many attractive features. However, depending on the application, it may not be the best solution. To achieve higher efficiency and lower circuit cost, it is sometimes necessary to think outside the box.