Implementation of external serial NOR Flash using QuadSPI

Preface

STM32 provides flexible and diverse access to external memory. This article will introduce how to use QSPI (QuadSPI) to expand the serial NOR Flash memory. First, the functional characteristics of the QSPI interface are introduced, and then the hardware design and software development are introduced respectively. And based on STM32CubeM, a reference for accessing MICRON N25Q128A13EF840F is provided.

1. Implementation Environment

Development board: STM32F469G-DISCO

Development library: STM32CubeF4 v1.16.0

STM32CubeMX: v4.22.0

Integrated development environment: IAR v7.70.1.11486

The implementation process is carried out on the STM32F469I-DISCO board, using the existing serial NOR Flash memory (MICRON N25Q128A13EF840F) on the board to present the entire development process. In this article, first, based on the QSPI interface, the hardware connection between QSPI and external serial memory is introduced. In addition, the Cube software package contains QSPI examples. This article does not discuss the QSPI examples implemented in the library. Readers can refer to these QSPI routines for design. This article focuses on the project generated by STM32CubeMX and introduces how to access the external serial NOR Flash memory.

2. QSPI Introduction

Before presenting an example of how to access external Flash using QSPI, you need to have a certain understanding of QSPI. Here is a brief introduction to QSPI. For more information, please refer to AN4760 .

QSPI (Quad-SPI) supports four-wire serial access. At the same time, QSPI supports traditional SPI and Dual-SPI modes, and Dual-SPI mode supports two-wire serial access. Compared with FMC/FSMC, QSPI supports lower cost, smaller package external serial Flash memory, less IO pins, effectively reducing PCB area and reducing PCB design complexity.

The following table shows the support of QSPI in different series of STM32 product lines (only a partial list, not covering all supported models).

The QSPI interface provides 5 flexible and configurable stages, as shown in the figure below (the timing diagram may vary depending on the configuration). They are the command stage, address stage, multiplexed byte stage, dummy stage, and data stage. The different stages can be configured according to the command timing in the external Flash. Examples will be presented later. For more information, please refer to AN4760 .

QSPI supports three modes:

Indirect mode  All operations are implemented through QSPI registers, similar to traditional SPI, and can be accessed using blocking mode, interrupt mode, or DMA mode for reading and writing. The implementation example provided in this article is an implementation in indirect mode.

Status polling mode  The interface automatically polls the specified register until the read-back register content matches the specified condition. It can be applied to status detection to achieve busy waiting and other effects. This article does not introduce this mode. For application implementation, please refer to the QSPI routine in the Cube software package.

Memory mapping mode  The external Flash is regarded as internal memory, supports direct access by AHB master devices, and the CPU can directly run the execution code located in the QSPI memory. The internal system architecture is shown in the figure below (taking STM32F469/F479 as an example). This article does not introduce this mode. For application implementation, please refer to the QSPI routine QSPI_ExecuteInPlace in the Cube software package.

Implementation of triple QSPI external serial Flash

3.1 Introduction to Serial Flash

Take MICRON N25Q128A13EF840F as an example. For more details, please refer to the memory manual. The pin diagram, timing diagram and electrical parameters of N25Q128A13EF840F are derived from the N25Q128A13 manual document.

Supported protocols: SPI, Dual I/O (corresponding to Dual-SPI), Quad I/O (corresponding to Quad-SPI)

Support access modes: single-line access, dual-line access, and quad-line access. Thanks to the flexible configurability of the QSPI interface, all three access modes are supported.

Supply voltage range: 2.7 ~ 3.6V

Maximum clock frequency: 108MHz

Storage: 128Mb (16MB)

The device pin diagram is shown below. It consists of two power pins and six QSPI signal lines.

The following table shows the memory N25Q128A13xxx commands (not all commands are listed). As can be seen from the table below, the memory provides a flexible access implementation, combined with the equally flexible and configurable QSPI interface, it can achieve full support for memory commands. This article only provides design ideas and presents the implementation of some commands on QSPI.

3.2 Hardware Design

There are few signal lines involved, and the hardware design is simple. You only need to directly connect the six signal lines of QSPI to the memory. Considering the testability, you can add serial resistors or test points. The hardware circuit diagram is shown below.

The QSPI interface PCB design follows the following points. For more information on hardware design, please refer to AN4488.

a. Line resistance 50Ω± 10%

b. Maximum line length <120mm

c. Avoid routing signal lines on different signal layers

d. The clock line should be at least 3 times the line width away from other signal lines

e. Data signal line length difference ≤ 10mm

f. Avoid serpentine routing for clock lines and minimize vias on data lines.

3.3 Software Development Process

3.4 Software Implementation Example

After the environment is built, you can use STM32CubeMX to configure QSPI according to the hardware connection and obtain the IAR project. The specific software implementation process is as follows.

Four conclusions

The QuadSPI interface of STM32 is flexible and configurable. It can be configured for the command stage, address stage, multiplexed byte stage, dummy stage and data stage. Based on this flexibility, it can realize the serial Flash support of SPI, Dual IO and Quad IO on the market. For the sake of simplicity, more functions such as interrupt access and DMA access supported by QSPI are not introduced in this article. For more implementations, please refer to the QSPI routines in the Cube software package provided by ST. In addition, the serial Flash commands and operation implementations of different manufacturers are slightly different. The specific description is subject to the Flash document description adopted.

Related Documents

AN4760 Quad-SPI (QSPI) interface onSTM32 microcontrollers

AN4488 Getting started withSTM32F4xxxx MCU hardware development

RM0386 STM32F469xx and STM32F479xxadvanced ARM®-based 32-bit MCUs

For more details about QSPI configuration and code interpretation, click " Read original text " in the lower left corner to download and read.

================================

Links to previous topics:

1. How to configure CRC parameters in IAR

2. A case of a computer crash caused by using an external SRAM

3. Leakage current analysis in STM32L4 STOP2 mode

4. Demonstration of using USB DFU to implement IAP function

5. Ways and means to obtain ST MCU technical information and related support