Major breakthroughs have been made in the research of post-quantum cryptographic chips, and the paper has been selected for ISSCC 2022 and CHES 2022

Yunzhong from Aofei Temple
Quantum Bit Report | Public Account QbitAI

Recently, the top international solid-state circuit conference ISSCC 2022 and the top cryptographic hardware conference CHES 2022 announced the selected papers. Muchuang Integrated Circuits has 1 paper selected for ISSCC 2022 and 2 papers selected for CHES 2022.

MuChuang Integrated Circuit has profound technical accumulation in the field of high-performance cryptographic chips. The three selected papers were completed by MuChuang Integrated Circuit in cooperation with Tsinghua University, respectively showing the company's latest research results in the fields of post-quantum cryptographic chips and fully homomorphic technology .

The paper "A 28nm 48KOPS, 3.4uJ/Op Agile Crypto-Processor for Post-Quantum Cryptography on Multi-Mathematical Problems" selected for ISSCC 2022 proposes a hybrid computing array architecture to address the problems of large computing and storage overhead, diverse and changeable algorithm types, etc. brought by the post-quantum cryptographic algorithms that NIST is about to standardize. This greatly alleviates the computing bottleneck caused by the introduction of position randomness and large-scale polynomial multiplication in cryptographic algorithms; and completes the development of the world's first post-quantum chip that supports algorithms based on different mathematical problems. Compared with existing embedded post-quantum chips, it supports more algorithms while achieving a 3.9x increase in energy consumption and a 232x increase in speed. The company's chief scientist Professor Liu Leibo and CEO Dr. Zhu Min are the main contributors to the paper.

The paper "CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Memory Mapping Scheme" selected for CHES 2022 proposes an efficient and low-overhead conflict-free address mapping method to address the problem of address conflicts caused by irregular access patterns in in-place NTT when implemented in parallel. Based on this mapping method, a scalable radix-2 and radix-4 NTT multiplication architecture based on an interleaved storage system is proposed as an acceleration engine for post-quantum cryptographic algorithms. The radix-4 NTT proposed in the paper has an area efficiency improvement of about 2.2 times compared to the radix-2 NTT multiplication architecture. The company's chief scientist Professor Liu Leibo and chief architect Postdoctoral Fellow Yang Bohan are the main contributors to the paper.

The paper "A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium" selected for CHES 2022 proposes an efficient and compact hardware architecture to address the problem that the post-quantum cryptographic signature algorithm Dilithium is computationally complex and has multiple unique functions, resulting in a large area and low computational efficiency of its existing hardware architecture. It is the world's first Dilithium algorithm hardware architecture that supports three security levels of key generation, signature, and verification at the same time. Compared with the highest security level recently achieved by similar platforms, it only uses 70% of LUTs, 73% of FFs, 33% of BRAMs, and 22% of DSPs resources, achieving 4.4, 1.7, and 1.4 times acceleration for key generation, signature, and verification, respectively . Professor Liu Leibo , the company's chief scientist , and Senior Engineer Wang Hanning , head of the Beijing branch , are the main contributors to the paper.

About ISSCC and CHES

ISSCC (IEEE International Solid-State Circuits Conference) is the highest-level conference in the field of integrated circuit design recognized by the world's academic and business communities, and is considered the "Olympic Games" in the field of integrated circuit design . Many milestone inventions in the history of integrated circuits, such as the world's first TTL circuit, the world's first 8-bit microprocessor, the world's first 1Gb DRAM, the world's first GHz microprocessor, and the world's first multi-core processor, were first disclosed at this conference.

CHES (Cryptographic Hardware and Embedded Systems) is a top academic conference on cryptographic chips and physical security hosted by the International Association for Cryptography (IACR) . It is also one of the conferences that the IACR industry focuses on. Electromagnetic analysis attacks, template attacks, correlation power consumption analysis, PRESENT algorithm, KATAN algorithm, etc. were all first proposed at CHES.