Power dissipation and heat dissipation analysis of high voltage gate drivers, get√ in one article
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Figure 1 shows a typical internal block diagram of an HVIC. The main functional blocks include the input stage, undervoltage lockout protection, level shifter, and output driver stage. The gate driver losses include:
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Static losses associated with quiescent current in the high-side and low-side circuits when the driver is biased and not switching.
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Dynamic losses associated with dynamic current when a switching signal is applied are related to the switching frequency.
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Gate drive losses, associated with the load switching charge, are directly dependent on the switching frequency.
Figure 1. HVIC block diagram
This article will not discuss the losses in the bootstrap diode, as the diode current is included in the dynamic losses. However, the instantaneous power loss during startup to charge the bootstrap capacitor cannot be ignored. During this period, a large current will flow through the diode, quickly charging the bootstrap capacitor and generating relatively high losses for several switching cycles. The bootstrap diode must be able to withstand these currents and power losses, which will increase the internal power loss of the driver when the diode starts.
Figure 2 shows a simplified schematic of the half-bridge switching network associated with the high-side and low-side drivers to explain the static losses.
Figure 2. Simplified circuit diagram of driver and half-bridge configuration for static power loss.
Static loss is caused by the static current from the DC voltage source V DD to ground in the low-side driver and the leakage current of the level converter in the high-side driver, as shown in the following equation.
Where I
QDD
is the quiescent current of V
DD
when there is no input switching signal
, V
BOOT
is the voltage on C
BOO
T, V
DBOOT
is the forward voltage drop on the bootstrap diode,
VR
is the rail voltage of the input power supply, and I
LK
is the leakage current on the bootstrap pin (
VB
pin
in Figure 2
). The quiescent power loss exists immediately after the driver is powered on and is independent of the frequency of the input signal.
However, most of the power loss occurs when the driver switches the power on or off. Therefore, I QDD is included in the switch-mode operating current, so P Quiescent should not be considered in this case . When ILK is small enough to be ignored or the V BOOT level is very high (such as 1200 V), P Leakage should be considered. If I LK is not provided in the driver data sheet , this loss can be ignored and is usually small compared to other losses.
Now let's consider the main loss sources. Figure 3 shows a driver circuit diagram that addresses the dynamic loss problem. The first type of dynamic loss is the loss in the high-side driver level shift (LS), or P LS .
Figure 3. Simplified schematic diagram of the dynamics and power losses of the driver and half-bridge configuration.
Q internal is the total gate charge of the internal L DMOS used in the level shifting circuit . Manufacturers usually do not provide the Q internal specification, so it cannot be found in the data sheet. As a rule of thumb, in this case, the Q internal value is about 0.6~1.5 nC for a 600 V high-side driver and about 0.4~1 nC for a 100 - 200 V driver. Some driver products using older technology may have relatively high Q internal values, so P LS should be considered when operating at high frequencies , but in the latest technology drivers, this value is getting lower and lower, and if the Q internal value is not provided , this loss can be ignored.
The second term, dynamic loss, is related to the output stage operating current powered by V DD and V BOOT . When the output stage drives external power devices, the dynamic loss (P OP ) is given by the following formula.
I DD is the operating current on V DD , and I BS is the operating current on the high-side driver pin VB. This power loss comes from the internal current consumption under dynamic operating conditions. The internal currents I DD and I BS should be determined under actual operating conditions with reference to the data sheet parameters and after considering the switching frequency.
If the data sheet does not provide I DD and I BS curves versus switching frequency, the following method is recommended to calculate I DD and I BS under given operating conditions .
If I DD (or I BS ) operates at 20kHz (F SW — DS ) at no load , then I DD (or I BS ) at 100kHz (F SW ) is approximately five times that of 20kHz because it is proportional to the switching frequency.
For a more accurate calculation, subtract the quiescent current from I DD or I BS before multiplying by 5 .
For example, the operating current ( IPDD ) at 20kHz in the data sheet is 0.5mA and the quiescent current ( IQDD ) is 0.05mA . The IDD at 100kHz is calculated using the following formula.
F SW is the target frequency and F SW_DS is the specified frequency in the data sheet.
If the load condition for I DD (or I BS ) is specified in the data sheet , such as a 1 nF capacitor, the current effect of the 1 nF capacitor can be eliminated by the following equation .
It should be noted that this formula is only a rough estimate, and the actual situation may be different depending on the specific parameters of the circuit and the operating conditions. In actual applications, it is best to perform actual measurements or use simulation tools to determine the exact current value.
C LOAD is the load capacitance specified in the data sheet
Figure 4. Simplified circuit diagram of driver and half-bridge configuration with gate drive power loss.
The gate drive loss in the driver is the maximum power loss caused by providing gate current at the switching frequency to switch the load MOSFET. The gate drive loss comes from the charging and discharging of the load capacitance (for MOSFET, the load capacitance is the input capacitance of the MOSFET) and is expressed as follows.
Where Qg is the total gate charge of the external MOSFET and fsw is the switching frequency. In a soft switching topology, Qg is equal to the gate-source charge (Qgs) of the FET or IGBT. Therefore, the total gate drive loss of the high-side and low-side drivers is 4 times Pcharging.
Since the main power loss is the gate drive loss, the simplest and quickest way to calculate the driver loss is to add the gate drive loss (Pgate_drving) and the dynamic loss on V DD . These losses account for more than 90% in medium voltage level high and low side driver products.
Once the power dissipated inside the driver is calculated, we can estimate the junction temperature of the driver. This can be evaluated based on thermal resistance or similar thermal design (heat sinking and airflow) characteristics. The thermal equation is as follows:
in
T J = Junction temperature of the driver chip
R jx = Thermal resistance (θ) or characteristic parameter (Ψ) that relates the temperature rise to the total power dissipated
T x = Temperature at point x as defined in the thermal characteristics table of the data sheet.
The thermal information is shown in Figure 5 and Table 1. The thermal characteristics of a package are a function of multiple parameters such as geometry, boundary conditions, test conditions, etc. This requires numerical analysis tools or modeling techniques, which are usually cumbersome to operate. It is very difficult to accurately estimate the junction temperature based on the thermal information in the data sheet.
Therefore, it is necessary to review the definition of thermal information.
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θja is the junction-to-air thermal resistance. Measures the heat flow between the chip junction and the air. Mainly applies to packages without any external heat sink.
-
θjc is the junction-to-case thermal resistance, a measure of the heat flow between the die junction and the package surface. Mainly applicable to packages using some external heat sink.
-
Ψ jt is a junction-to-package top thermal characteristic parameter that provides the correlation between the die temperature and the package top temperature. It can be used to estimate the die temperature in the application
-
Ψ jb is a junction-to-board thermal characterization parameter that provides the correlation between the die temperature and the board temperature. It can be used to estimate the die temperature in an application.
Figure 5. Thermal resistance and characteristic parameters of the package.
Table 1. Definitions of thermal resistances and characteristic parameters.
Generally speaking, the thermal information provided in semiconductor data sheets does not cover all application scenarios. In the following example, we only use θja to calculate Tj.
If Tj is too close to the recommended operating temperature, the following situations may be considered.
1. Add external gate resistors to spread power loss: If no external gate resistor is inserted between the driver and the MOSFET, the power will be completely dissipated inside the driver package. Using an external gate resistor can share the power loss between the internal gate resistor of the driver and the inserted external resistor. The sharing ratio is determined by the ratio between the two resistors. The larger the external gate resistor, the smaller the power loss inside the driver.
2. Reduce the switching frequency. The switching frequency has the greatest impact on power loss, so it can be reduced as long as the application allows.
3. Use a heat sink. Expand the PCB area and add copper around the driver.
4. Reduce the supply voltage VDD as much as possible . The latest generation of drivers and MOSFETs offer this option.
Reducing the switching frequency or supply voltage is not always possible, and there are often limitations to expanding the printed circuit board or adding heat sinking. Most of the time, people use external gate resistors for various reasons, such as limiting ringing caused by parasitics or high dV/dt, and adjusting the gate drive strength to reduce EMI. This also has an impact on the power loss distribution. After adding the external gate resistor, the gate drive power loss is calculated as follows:
Where RON and ROFF are the internal pull-up and pull-down resistors , and Rgon and Rgoff are the external gate resistors. In simple terms, if RON = ROFF = Rg , Psw will be half the total power dissipation compared to without the external gate resistor .
Figure 6. Internal pull-up and pull-down resistors.
Taking NCV51511 as an example, according to Vdd/peak pull-up (or pull-down) current, R ON is 2 Ω and R OFF is 1 Ω. If 1 Ω is inserted between the output pin and the MOSFET gate, the gate drive loss will be reduced to 83%.
The white paper also introduces the power loss in the level conversion circuit, the power loss calculation and thermal estimation of NCV51511, and the application on FAN73912. Please scan the QR code to download the full version of the white paper.
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