How does a three-phase PFC converter significantly increase the charging power of an on-board charger (OBC)?

Here, the output voltage provided by the three-phase PFC is fixed at 700 V (accuracy 5%). Thanks to SiC technology, the thermal capacity can be extended to a higher range. Taking an input voltage of 50 Hz and 230 Vac as an example, the maximum deliverable power is 11 kW.

▲ High fs range (60−140 kHz)

▲ High efficiency (98.3% at fs 100 kHz)

▲ Wide input range (167 - 265 VPH rms)

▲ Two-way

Figure 1: Board picture

Figure 2: Topology - Overview

Figure 3: Three-phase PFC block diagram

The general concept can be seen in Figure 3. Since testability was set as the highest priority during concept definition, the boards provided do not target the highest power density and/or compactness.

当向输入连接器提供 50Hz 的三相电压时，板的行为很简单；由于 PFC 拓扑的性质，输出总线电容电压会升高。由于每个 MOSFET 上都存在寄生续流二极管，带有 MOSFET 的无桥 PFC 保证了从输入到输出的电流路径。当 MOSFET 全部关断时，电路板简化为三相二极管桥。整流后的输入交流电压将根据电源电压幅度和 MOSFET 体二极管的正向电压，被设置为定义的电平。然而，输入端至少要提供一个 167 Vrms 的电压。因此，两个不同线路上的电阻用作浪涌电流限制器。一旦总线电压达到 400 V，双管反激变换器便开始工作。它提供 24 V 电压。藉此，一系列 DC/DC 稳压器可生成为数字和模拟电路供电所需的其他电压电平。

During micro-wakeup, in addition to verifying the offset voltage of the ADC channel, it also begins monitoring the bus voltage and detecting the input voltage to determine the frequency and phase angle of the voltage. This phase angle will be used as the base angle for the system to achieve power factor correction.

When the DC bus voltage reaches a flat state, the MCU sends a command to the relay, bypassing the resistor and allowing the output bus voltage to increase further. However, the voltage increment will be lower than the rectified input voltage amplitude of √6∙V _{PH, RMS} .

The MCU will wait until the bus voltage is flat again so it can start controlling the bus voltage until it reaches the target value of 700 V. It does not reach the target value in one step, but follows a smooth ramp generator that changes the bus voltage value according to a parameterized ramp to the final 700 V.

PFC implements only one hardware protection, using the DESAT function of the NCV51705 gate driver to prevent over-current events. Based on the characteristics of the NVHL080N120SC1 silicon carbide MOSFET (N-channel, 1200 V, 80 m, TO247-3L), a threshold of 50 A will be set on the board.

All faulty lines are brought together to generate a single input to the MCU, which will provide a hardware stop for PWM generation. Fault conditions can only be reset via a reset command sent from the GUI or via a power-off/power-on sequence, which typically represent a hardware/software reset respectively. Figure 4 summarizes the overall behavior at the software level.

Figure 4: Flow chart of preliminary steps before activating DC bus voltage regulation

Once the application is in DC bus voltage control, in the absence of a fault event, the MCU will execute the Field Oriented Control (FOC) voltage control algorithm.

The control algorithm is similar to the motor control algorithm in that the inner loop controls the current component and the outer loop controls the bus voltage. Since the goal of PFC is to ensure that the phase delay between each phase voltage and phase current is 0°, the voltage regulation will act on the D-axis current. The Q-axis current is set to 0. The D-axis represents the "ACTIVE" power branch, while the Q-axis represents the "REACTIVE" power branch. Figure 5 shows the block diagram of the control algorithm.

Figure 5: Control block diagram

Analog quantities sampled to execute control algorithms include:

Line voltage is used to determine the actual position of the AC voltage phasor. Then, the angle θ is used to adjust the current phase delay to 0, which is the main goal of PFC. The voltage positions are used to transform from the stationary ABC system reference to the rotating DQ coordinate system (for PFC, the D-axis represents the amplitude of the phase voltage phasor) via Clark and Park transformations.

With θ known, all quantities can be represented in a DQ system, and this simplification will ensure that a simple PI/PID regulator can be used. By the way, PID stands for Proportional Integral and Derivative Regulation, which can be applied to a system individually or in combination. In either case, the correct choice depends on the transfer function of the device to be adjusted.

When a constant is available as a reference, the PI regulator can indeed effectively adjust the error to zero, but it cannot adjust the AC reference. In any case, the PI regulator needs to be calibrated to ensure proper system stability and a reasonable trade-off between PI loop bandwidth and time response. It is generally expected that the current loop (inner) will respond faster and the outer loop (voltage) will respond slower.

Figure 7 provides a detailed diagram of the implemented control loop. Regardless of the PWM modulation frequency selected, the control loop will run at 20kHz. Although synchronization procedures exist to cause the ADC peripheral to be triggered by a specific PWM counter value, the PWM frequency is almost independent of the control frequency.

This procedure allows to maintain a good relationship between the phase currents, in a star-connected three-phase system with an isolated neutral point, the instantaneous value of the sum of the currents should be equal to zero.

The selected MCU is a general-purpose MCU based on Arm ^® M3, clock frequency 84 MHz, single S/H and ADC with multiplexed input channels, 1 MSPS and 12 bits. The latency of one ADC conversion is about 1 μs.

由于读取延迟、快速 PWM 频率、瞬时开关状态和升压电感等原因，每个相位中流动的电流可以在极短的时间内发生显著变化。因此，为了克服这种有问题的情况，系统会在三个连续的 PWM 周期内对电流进行采样。这意味着可用于相应功能的最小 PWM 频率是控制策略的三倍，也就是 60kHz。当然，所允许的最大 PWM 频率也存在限制，即 140 kHz。再次触发 ADC 外设进行新的测量之前，在每个 PWM 周期中执行测量所需的等待时间会引入该限制。图 6 显示了这种限制背后的原因。

Figure 6: Main peripheral interaction and control algorithm execution

As can be seen from Figure 6, a new ADC trigger can only be issued when the following conditions are met: three analog quantities (1 current and 2 voltages) have been sampled; the ADC's conversion end interrupt has been sent to the CPU (to store the result data register into memory); the ADC is ready for a new measurement. Each procedure takes approximately 3.5 μs. After three PWM cycles, the ADC is no longer triggered until a new control interrupt occurs to reinitialize the read strategy.

Analog quantities collected during the control period will be used in the next available control period. There is a deterministic delay between the time the analog is sampled from the ADC and the time the analog is effectively used in the control strategy. However, this delay is not compensated because the main operating frequency is much lower than the selected control frequency period, so the delay is considered negligible.

Once the ADC analog is available, control is much simpler, as shown in Figure 7.

Figure 7: Control algorithm details

As mentioned before, the modulation frequency can be selected in the range between 60kHz and 140kHz, which is the benefit of using silicon carbide MOSFETs. Of course, from a system behavior perspective, increasing the switching frequency will mean higher switching losses, which will essentially lead to an increase in chip temperature, thereby increasing conduction losses. The reason is that R _DS,ON will change with temperature. increase. It is for this reason that it is foreseeable that there should be a fan on the board, the purpose of which is to cool down the heat sink where the SiC MOSFET is located. The fan is driven by the MCU, but for now its speed will be fixed. The fan speed can be adjusted based on the effective power delivery proportional to I _{D, REF .}

To mitigate losses and increase system efficiency, different driving strategies can be implemented. Further details are provided in the results section.

This system consists of two boards: a 4-layer power board and a 4-layer control board.

The power strip will be embedded with:

Predictably from the layout of the relay: when powered up, the 13.6 power resistors mounted on the board limit the inrush current. The resistor can be disconnected by toggling the INRUSH_OFF pin to set the digital value high. On power-up, this pin is initialized low.

There are six symmetrical gate drivers on the board. Each of them contains an isolated DCDC converter, a digital isolator and NCP51705 gate driver. NVP51705 is a dedicated device used to drive SiC MOSFETs. Each part has 3 digital pins: 2 inputs and 1 output (this is from the gate driver's perspective; if you're looking at it from the MCU's perspective, it's 2 outputs and 1 input). The MCU must provide a disable signal for each driver; it actually represents the inverted input of the PWM signal and the PWM signal itself. The MCU must detect the faulty pin. It represents a fault condition of the gate driver level.

Once a gate driver fault is established, it automatically disables the PWM output. The fault pin is used to signal fault status to the MCU. This fault is usually caused by an overcurrent event, although other abnormal conditions may trigger this fault.

Once a fault event occurs, the PWM signal is no longer supplied to the gate driver and the DISABLE pin becomes active again.

The fault pins of each gate driver are grouped into the "or" port, with a total of six inputs. The generated PWM_FAULT is then connected to the available hardware PWM fault pin on the MCU.

The DISABLE pin should be initialized to HIGH to disable the gate driver functionality. When the control strategy is able to send valid duty cycle information, DISABLE must be set low.

The system will generate the following test results, supplying 230 Vrms at 50Hz to the board.

The control algorithm is configured to provide a switching frequency of 100 kHz and a dead time of 100 ns. The boost inductor used has an average inductance value of 330H.

The gate resistor values ​​used to drive the MOSFET are 22 Ω (for source) and 4.7 Ω (for drain) to ensure the following switching characteristics at maximum current:

Different PWM strategies should be implemented and tested for different situations. Each strategy affects the inductor high-frequency current ripple, while the low-frequency envelope follows the output power target. Although the current ripple is related to the PWM frequency and bus voltage, it is also heavily affected by the zero sequence voltage. The zero sequence voltage affects the voltage generation across the inductor during the PWM cycle.

Finally are the system efficiency results of running the PFC board at 100kHz with the "Discontinuous 1" modulation strategy selected.