How to improve simulation level? You need to learn to generate LTspice models yourself

After testing the circuit, I found many differences between the actual circuit and its design. The dynamic characteristics of the circuit are a bit unexpected, and its noise level is much higher than required. I need to simulate the circuit with a simulator to fully understand it.

This circuit uses an analog switch and an op amp. The op amp has a well-established macromodel, but the analog switch macromodel is not a common type. The switch macromodel file header states that the model parameters are only valid for a specific supply and temperature. Well, you might not know this: my circuit does not operate under the same conditions as the circuit model. The thing about analog switches is that they are so common that a specific parameter model is not enough. Existing industry standard models provide a good starting point, but when it comes to analog performance, you may need to take a new macromodel approach to advance your simulation.

When I started looking at the various analog switch macro models available from ADI and other IC companies, I discovered that none of them modeled dependencies on power or temperature. So I had to build my own macro models.

During construction, I decided that all the behavior to be simulated should be provided by all the transistors in the analog switch using the simplest device model, but the interface connecting the control pin and the MOS gate should be the simplest behavioral element. This was done using the LTspice simulator, and the code can be used on other simulators as long as the LTspice behavioral devices are converted to SPICE-like polynomial functions. We will simulate in a specific order.

We will use the simplest model to simulate a real MOS device. To model the on-resistance, we will use:

• W/L, width (W)/length (L) of MOS device. W/L indicates the size or relative strength of the device.

• V _TO , threshold voltage; gamma (γ), uses the device's back bias to change V _TO . The back bias is the voltage difference between the turn-on device and its body voltage; the body is usually connected to the positive supply of the PMOS in the switch and the negative supply of the NMOS.

• ^{_{K P}} , also called K' or K-prime in the model. This parameter simulates the strength of the process and is used to adjust the MOS current after multiplying by W/L. In a given process, the K _P is generally about 2.5 times that of PMOS.

• ^{_{R D}} , parasitic resistance of the device drain.

Different MOS processes use different internal parameters. Table 1 summarizes common CMOS processes, their characteristics, and estimated values ​​of internal parameters related to on-resistance.

Table 1. Typical semiconductor process parameters

Consider the ADG333A R _ON curve in Figure 1 that we would like to reproduce .

Figure 1. R _ON as a function of VD(VS) (dual supply).

In this and other analog switches, we see a general trend: higher supply voltages reduce on-resistance. When higher voltages are applied to the switch MOS gate, on-resistance decreases. We also see that on-resistance varies significantly with input analog signal levels. In the N region, the NMOS transistor in the switch is fully turned on, and when the analog voltage is above the negative supply rail, the PMOS transistor turns on, helping to reduce the overall on-resistance. The turning point in region N is roughly at the PMOS VTO above the negative _supply .

Likewise, in region P, when the PMOS device of the switch is fully turned on, approximately at NMOS VTO below the positive supply _, the NMOS device begins to assist the PMOS transistor.

Region M is between regions N and P, where NMOS and PMOS act in parallel, but with different on-resistances, which are determined by the analog signal levels within the power rail.

To start the curve fitting process, we first estimate the size of each transistor. The low voltage curve provides the best curve fit for the transistor R _DS,ON . In region N, when the analog signal is within the negative supply voltage range, the PMOS device is off and the R _{ON of the part is equivalent to the R ON} of the NMOS transistor . Where

_{We use the typical process values ​​for 40V NMOS and set R DS,ON = 38Ω} according to the curve in Figure 1. Using the given process values, we find that WNMOS = 2µA/(38Ω×(11×10 ^–6 µA/V ² )×(10V–0.7V)) = 514µm. The on-resistance of the PMOS switch on the upper curve is 47Ω and the width is 936μm.

I used the LTspice test circuit in Figure 2. Note that the parameters R _DN and R _DP , the parasitic drain resistance, are moderate values. I initially used a value of 1μ, which caused the simulator to converge slowly. An R _DN value of 1 gave normal simulation speed. Adding _{R CONVERGENCE} provides a converged conductance to the switch node, improving simulator noise and speed. I tested a floating current source to measure the on-resistance.

Figure 2. On-resistance test circuit.

Figure 3 shows the simulation results under various power supply conditions.

Figure 3. On-resistance simulation results using initial model values.

This is a pretty good start. The simulated kink point is 3.6V at VS = 30V on the low side, but 2.7V in the datasheet. It can be seen that we should reduce the PMOS VTO _, but 0.9V is actually the minimum. It would be better if the PMOS gamma could be adjusted, but this is just a guess.

The kink point near maximum supply is 2.5V below the 30V rail, which should be ~1V in the datasheet. Various gamma values ​​will amplify the kink voltage from the rails; we will set the NMOS VTO _to 1V and its gamma to 0. A gamma of 0 is a bit unexpected, but we are just trying to curve fit. Figure 4 shows the simulation results when the gamma of the PMOS is stepped at several supply values. We will focus on the 30V curve, which maximizes the effect of gamma compared to the lower supplies.

Figure 4. On-resistance simulation results for different gamma-p values.

According to the step curve, we choose PMOSgamma=0.4.

Regarding R _ON , it can be seen that the 10V curve represents the corresponding data sheet curve at the supply extremes (limits), but for the 20V and 30V curves, the simulation produces too low R _ON . At the negative supply extreme, R _ON s= R _DS,ON (NMOS)+R _D (NMOS), and at the positive supply extreme, R _ON s=R _DSON (PMOS)+R _D (PMOS). For high voltage supplies, the R _D parameter is more important than W/L, and for low voltage supplies, W/L is dominant. We will use two variables here; this is very time-consuming and labor-intensive. We will assume that R _ON varies with supply, because different levels of enhancement are applied to the NMOS, but the R _D value does not vary with supply voltage (well, it may vary in drain drift, but let's keep it simple). If we notice the difference in the data sheet R _ON between 10V and 30V supplies (11.4Ω), we can compare it to the curve above using only W _N (the width of the NMOS in the switch). After some iterations of the simulation on W _{N , it is clear that we need W N} = 1170µm to achieve the desired ΔR _ON , which is significantly higher than the initial guess. Figure 5 shows our current results.

Figure 5. On-resistance simulation results when W _{N is determined.}

Although the NMOS R _ON has the correct power supply sensitivity, at 0V, the curve is still too low and we must increase the fixed R _DN . After increasing and iterating R _DN , we obtain the optimal value, R _DN = 22Ω, and the corresponding curve is shown in Figure 6.

Figure 6. On-resistance simulation results when R _{DN is determined.}

We then determine W _P (the width of the PMOS in the switch) to simulate R _ON at maximum voltage and obtain WP = 1700µm, which is also much higher than the initial guess. Setting R DP to 22Ω as well, we obtain the final R _ON curve shown in Figure 7 .

On-resistance simulation results when W _P and R _{DP are determined.}

The agreement is very good; only a few characteristics differ from the datasheet. One is that the turning point is very gentle in the datasheet curve, but quite sharp in the simulation. This is probably because the simple MOS model used does not support subthreshold conductivity, and the simulated device actually turns off at ^V _TO ^{from the supply rail. The real device does not turn off at V} _TO , but rather smoothly reduces the current at that voltage.

Another error is very obvious in the 30V curve. Compared to the datasheet, R _ON is 15% lower at mid-voltage. This is probably due to the JFET effect in the drain drift region, which is also not simulated in the model.

As for the temperature, it is relatively consistent, but the degree of consistency is not very high. Please refer to Figure 8 for details.

Figure 8. On-resistance simulation and data sheet results at various temperatures.

The simulation results are temperature dependent, but not as temperature dependent as the data sheet curves. In the simulation model, R D has no temperature coefficient. R D S can be simulated with an external resistor and the correct temperature coefficient, but for simplicity we will not consider it.

When a MOS transistor is turned off, the charge in the channel has to go somewhere, so it escapes from the drain and source terminals. When an analog switch is turned off, charge also escapes, which is called charge injection. A common measurement method is to set a fixed voltage on one end of the turned-on switch and a large capacitor on the other end. When turned off, the capacitor captures the charge and a small voltage step occurs. Now, we add the gate oxide thickness T _OX =1×10 ^–7 to the MOS model (the gate capacitance is the largest source of charge injection). The simulation setup is shown in Figure 9.

Figure 9. Charge injection simulation setup.

The data sheet charge injection test circuit sets the voltage source at the D terminal of the switch and the capacitor Cl at the S terminal of the switch. When the switch transistor is off, Cl is isolated and the charge injected into it is integrated through the switch. In this case, the V _D waveform is maintained at 24V when the power supply is 30V, as shown in Figure 10.

Figure 10. Charge injection simulation waveform.

The injected charge is the voltage jump between V(S) and V(D) multiplied by the 10nF holding capacitor. We can implement a switch voltage V _D step across the supply voltage range and use the .meas statement to capture the charge injection value at each voltage. Figure 11 shows the data sheet curve results and the simulation results.

Figure 11. Charge injection data sheet and simulation waveforms.

Our simple MOS model does not simulate the data sheet curve waveform very well, but in the data sheet curve, the peak charge injection value is 32pC, and in the simulation it is 31pC. Surprisingly, these two values ​​are very close, and if necessary, we can adjust T _OX to improve the simulation results.

There is an offset between the two curves, which we can compensate for using C _{CHARGE_INJECTION . After some value adjustments, we choose the optimal value C CHARGE_INJECTION} = 0.28pF. If a reverse polarity offset is required, _{C CHARGE_INJECTION} is reconnected to the PMOS_on_when_low node.

Adjusting the capacitor _{C CHARGE_INJECTION} is a convenient way to offset the simulated curve of charge injection versus analog voltage. What if the simulated peak injection value is too small? Well, most of the charge injection will cause the gate voltage of the switch to swing, sending charge through the gate channel capacitance of the switch transistor. If the simulated injection is too little, we can simply increase the area of ​​one or both gates. To do this, we need to increase the parameter values ​​of the switch device, L and W, by the same factor, while ensuring that the W/L ratio that sets the on-resistance is not changed. Instead of using _{C CHARGE_INJECTION} , we will choose to increase the NMOS W and L.

Alternatively, we could adjust T _OX for each device to get better charge injection correlation results. This is not practical, however, we are only simulating this. In the simple model we use, T _OX does not affect other simulation parameters.

With the parameters set up to get good R _ON and charge injection simulation results, we can now simulate the S and D terminal capacitances.

An important point is that both drain and source regions of a high voltage MOS switch must have an offset region. For a switch, you cannot distinguish the functional difference between source and drain, but both the body potential of drain and source require their own offset regions. This is also true for medium voltage soft diffusion, but it is not reasonable in low voltage MOS. We have aggregated the offset region resistance present in drain and source into R _D , which is valid for switches but not for transistors in saturation.

Figure 12 shows the simulation setup.

In LTspice you can run the .ac at one frequency (using the options listed in the .ac), but only one frequency parameter (1MHz in this case). You can then run the .step V _SOURCE dc voltage over the entire supply range to get a curve of capacitance vs. voltage range.

The D terminal of the off switch device is held at mid-voltage. The S terminal (renamed here to prevent confusion with VS) is driven by a voltage source with a DC value range of 0V to VS _and an AC drive voltage of 1V. The capacitance is calculated as I(V _SOURCE )/(2×π×1MHz×1V). The logic drive V1 is changed to 0V to turn off the transistor.

In the model description, the drain capacitance and source capacitance are C _BD and C _BS , respectively . The model includes built-in default concentrations, built-in voltages, and exponents to make the CBD and CBS voltages variable. Because they are symmetrical, the drain and source capacitances can be equal. In addition, because the width of PMOS is different from that of NMOS, the ratio of C _BD,NMOS/ C _{BD ,PMOS} =C _BS,NMOS /C _BS,PMOS ≡W _N /W _P is determined in the on-resistance model. Figure 13 shows the simulation results.

Figure 13. Off capacitance vs. DC voltage for VS = 12 V (left) and 30 V (right).

The result displayed is I( _{^{V SOURCE}} )/(2×π×1MHz), which represents capacitance. LTspice does not know what this value means and displays pA instead of pF.

Unfortunately, we don't have data sheet curves to compare. From the data sheet specs table, it appears that the capacitance (perhaps at mid-voltage, which is not specified in the data sheet) is typically 7pF at 30V supply voltage and 12pF at 12V supply voltage. I adjusted C B to get a 7pF curve at 30V, but could only simulate a 10pF curve at 12V. After adjusting the internal potential and the capacitance formula exponent, the model used could no longer improve the 12V/30V compliance.

Figure 14 shows the capacitance simulation setup for the on state.

Figure 14. Simulation setup for capacitance test in the on state.

It can be seen that the right switch of the complete SPDT switch is turned on, and the left switch is turned off and connected to the Vs / 2 source. The right half capacitance of the left switch is in parallel with the total capacitance of the right switch and the parasitic capacitances present at the D and S terminals, driven by the 1MHz test signal of the V_s source, whose DC level is stepped from ground to Vs. Figure 15 shows the simulation results.

Figure 15. Turn-on capacitance vs. DC voltage for VS = 12 V (left) and 30 V (right).

The simulation gives values ​​of 29.5pF and 21.4pF, while the data sheet gives values ​​of 26pF and 25pF. We believe these values ​​are very close, taking into account the variation in capacitance due to the board layout.

The data sheet curves show pA leakage current as a function of voltage at 25°C, but the data sheet specification only guarantees a few hundred pA. I am more influenced by the curve results at 25°C. For this device, the importance of small leakage currents is not properly understood, so the test results cannot be guaranteed. Objectively speaking, measuring a pA leakage current requires a lot of design development work and long test time.

At 85°C, a few nA are guaranteed (valid for measurement), and typical values ​​are in the hundreds of pA range. I consider these typical values ​​to be fairly accurate.

Leakage current is a product defect; there is no strict statistical data and it varies greatly with temperature. It is not a specification we design to, but rather a value that will interfere with the circuits it is connected to. When used in a macro model, leakage of the right magnitude will simulate as a circuit defect and serve as a good warning to the designer. I chose a target test value of 1nA at 85°C for the on-state switch.

Our model shows no leakage current that exceeds R _CONVERGENCE and _{G MIN . G MIN} is a resistor placed between the junctions by the simulator to aid convergence. Its conductance is typically 1×10 ^–12 but with a supply voltage of 30V, this can be several times the 30pA current, far higher than required for testing. In a range of simulation options, G MIN is reduced to 1×10 ^–15 and R _CONVERGENCE is increased to 1×10 ¹⁵ .

Most of this leakage is likely to actually come from the electrostatic discharge (ESD) protection diodes connected to each pin. We will include this in the simulation setup of Figure 16.

Figure 16. Leak test simulation setup.

_{After adjusting l s} in the diode model , we obtain the leakage current vs. temperature curve, as shown in Figure 17.

Figure 17. Leakage test simulation results over temperature range.

A simple behavioral logic-gate drive circuit is shown in FIG18 .

Figure 18. Behavioral logic-gate interface.

The external logic input is at the input terminal on the left side of Figure 18. It is the input to the ideal transconductor Glogic_thresholda, which has a piecewise linear transfer function. For logic inputs below 1.37V, the output under the logic node is 0V; for inputs above 1.43V, the logic output is 1V; between 1.37V and 1.43V, the logic output transitions linearly from 0V to 1V. Glogic_thresholda thus ignores power supply differences and provides a 1.4V input threshold.

Cdelaya will slow down the logic node for a moment, so we can capture some time points. To make the comparator, we use transconductance again. This time, the output of Gbreakbeforemakena again transitions from 0V to 1V, but the threshold swings slightly above 0.5V. As can be seen in Figure 19,

Figure 19. Break-before-make timing.

The ramped action voltages are 0.52V and 0.57V instead of 0.5V, which allows an exponential signal falling from 1V to turn off faster than an exponential signal rising from 0V.

The full gate drive voltage is generated by B_non and B_pon behavioral current sources. When node n_breakbeforemakena>0.5V, B_nona generates V _{DD /1000 current and the voltage of node nona reaches V DD} when loaded with 1000Ω resistor . When node n_breakbeforemakena<0.5V, node nona is driven to V _ss . So, we have a nice rail-to-rail gate driver that meets the supply voltage requirements and has a fixed input threshold of 1.4V.

There is one more feature we need to note. Notice in Figure 20 that higher supply voltages reduce the delay. This is accomplished by B_supplysensitivitya, which returns a small amount of its own dynamic current to Cdelaya that varies with V _DD . Rsupply_sensitivitya sees a small voltage drop across the Cdelaya current, causing Cdelaya to act largely as a pure capacitor. Returning a copy of the Cdelaya current back to Cdelaya actually creates a controllable variable capacitor, and the math inside Bsupply_sensitivitya actually produces the delay vs. V _DD curve shown in Figure 20.

Figure 20. Break-before-make timing results for simulation and data sheet curves.

Our circuit simulates a TON delay of 111ns at VDD ₌ 4V, while the datasheet curve shows a delay of 140ns . At _VDD = 15Vs, the simulated delay is 77ns, while the datasheet delay is 60ns. Not much correlation; I'll leave it to the reader to refine the Bsupply_sensitivity function to achieve better results. At least, the difference in break-before-make timing would be better between 15ns and 24ns.

Although the data sheet does not give much information about the relationship between delay and temperature, I added a temperature term in Cdelaya and found that at least under high temperature conditions, the model simulation speed slows down, as shown in Figure 21.

Figure 21. Timing delay vs. temperature.

Figure 22 shows the combined analog switch that will become a branch circuit. In place of the transistor symbols are L and W hardness values ​​instead of parameters, and all excitation and I/O are removed to connect pins SA, D, SB, In, V _DD , V ss , and Gnd_pin.

Figure 22. Combined SPDT branch circuit spdt 40V.asc.

A second logic interface is also provided for the other switch of the SPDT pair. ESD protection diodes are placed between the analog port and V _ss , and between the logic input and ground. Note that the "-a" suffix in the upper logic interface device and node names is replaced with a "-b" suffix in the lower interface. The output of the Glogic_thresholdb interface is the inverse of the output in the Glogic_thresholda table, allowing one or the other switch pair to operate, rather than both being on at the same time.

Alternative ESD protection schemes include diodes from the protected pin to V _DD and V _ss , and a clamp between V _DD and V _{ss . The data sheet usually provides a description of the protection scheme, and the leakage current is divided between the two supplies.}

In the main ADG333A.asc schematic shown in Figure 23, the symbol for the SPDT branch circuit is given and used four times.

Figure 23. ADG333A macromodel circuit schematic.

Figure 24 shows a schematic diagram of the test structure used to verify the final macromodel results.