Chip Testing Lecture Series——MIPI D-PHY

MIPI Alliance is the Mobile Industry Processor Interface Alliance (MIPI for short). It was established in 2003 by ARM, Nokia, ST, TI and other companies to develop an open standard and specification for mobile application processors. At present, MIPI has become the most mainstream video transmission interface specification in the mobile field. The most widely used are the two groups of protocol clusters MIPI D-PHY and MIPI C-PHY. Many modules in C-PHY are borrowed from D-PHY. The two standard interfaces can share the same pins to achieve dual-mode. As for MIPI M-PHY and A-PHY, we will share more in subsequent articles.

There are different WorkGroups under the MIPI Alliance, which define a series of internal interface standards for mobile devices such as mobile phones, such as the camera interface CSI, the display interface DSI, the DigRF interconnection between BBIC and RFIC, the microphone/speaker interface SLIMbus, etc. MIPI technology is layered, including the physical layer, protocol layer and application layer. The same PHY physical layer can carry different protocols. The following figure is the MIPI system block diagram and multimedia specifications:

Figure 2: MIPI Multimedia Specification

From MIPI Alliance official website

The two most mature MIPI application interfaces are as follows, and their protocol layers are CSI-2 and DSI/DSI-2 respectively.

Figure: From MIPI Alliance

D-PHY realizes the interconnection between Camera/Display and AP (application processor), and has the characteristics of high speed, low power consumption and low cost. It is not only suitable for mobile applications, but also for IoT. D-PHY provides a source synchronous interface between master and slave, including 1 pair of unidirectional differential clocks, supporting SSC, 1 to 4 pairs of unidirectional or bidirectional differential data lines. Data transmission adopts DDR mode, that is, data transmission occurs on the upper and lower edges of the clock. The following figure is the Two Data Lane PHY Configuration of D-PHY:

Figure: D-PHY Two Data Lane PHY Configuration

The physical layer of D-PHY supports two working modes: HS (High Speed) and LP (Low Power). In HS mode, low-voltage differential signals are used, with terminations, and can transmit very high data rates (data rates are 80M~1.5Gbps/without skew cal, 1.5G~2.5Gbps/with deskew cal, 2.5G~9G/with equalization); in LP mode, single-ended signals are used, without terminations, and the data rate is very low (<=10Mbps), but the corresponding power consumption is also very low. Considering EMI, the generated signal slew-rate and driving current are limited. The optional alternate low-power mode uses terminated low-voltage differential signals, with a minimum forward data rate of 4Mbps and a minimum reverse data rate of 1Mbps, and the maximum is consistent with the HS rate. The combination of HS and LP modes ensures that the MIPI bus can transmit at high speed when a large amount of data (such as images) needs to be transmitted, and can reduce power consumption when large amounts of data are not required.

Figure 1 below is a schematic diagram of the signal levels in HS and LP modes, and Figure 2 below is a MIPI D-PHY signal captured by an oscilloscope, where the HS and LP signals can be clearly seen.

Figure 1: Signal levels in HS and LP modes

Figure 2: MIPI D-PHY signal captured by oscilloscope

Although the board-level design of MIPI D-PHY is simple, the internal architecture and I/O technology of MIPI chips are very complex. The complexity is reflected in the following aspects:

Because of the complex internal composition and electrical architecture, it takes very complex tests to ensure the interoperability of interface signals. MIPI Alliance has developed the Conformace Test Suite (CTS) to optimize the interoperability of products based on MIPI Spec. It examines the physical layer functions (not performance) and is different from compliance test (all items must pass). The more items that pass the interoperability test, the more confident developers are, indicating that the product can work properly in many MIPI usage environments.

Taking physical layer testing as an example, transmitter testing is mainly based on oscilloscopes, and receiver testing is based on high-speed arbitrary waveform generators. With the help of automated protocol analysis and decoding software, the debugging and testing efficiency can be greatly improved. The following section will introduce the physical layer testing in detail.

The main test items involved in MIPI D-PHY physical layer test include (according to mipi_D-PHY-v2-1_CTS_v1-0):

Among them, Tx test is completed based on oscilloscope and automated test software, Rx test is completed based on high-speed arbitrary waveform generator, and S parameter impedance test is completed based on network analyzer or TDR, as summarized in the following figure:

Figure: Summary of MIPI D-PHY physical layer test solution

Tx testing is mainly based on oscilloscopes and automated software. According to the rates and specification parameters of each version of MIPI D-PHY, an oscilloscope with a suitable bandwidth needs to be selected. According to the requirements of the MIPI Association, the bandwidth of MIPI versions of oscilloscopes with different rates and the selected automated testing software are as follows:

Figure: MIPI D-PHY Tx test oscilloscope bandwidth and software recommendations

For the testing of MIPI chips or modules, the evaluation board TVB (Test Vehicle Board) can be designed according to the method recommended by the MIPI Association to convert the signal output into a standard SMA interface output, and the signal test can be performed in combination with the RTB (Reference Termination Board) provided by the Association. The RTB board provides standard matching switching and different line capacitance options, as shown below:

Figure: Based on TVB (Test Vehicle Board)

MIPI D-PHY chip or module testing

For system manufacturers such as mobile phone manufacturers, since the system design has been completed, the MIPI signal test can only be carried out by using welding or spot probes to connect to the actual signal on the PCB for testing. The following is a typical connection diagram:

Figure: MIPI D-PHY board-level test connection

In order to improve the test efficiency, it is recommended to use 4 probes to connect the clk+/clk- and data+/data- signals for testing. The reason why two probes are needed for each differential pair is that there are two modes, HS and LP, on the D-PHY signal line, and the termination methods of these two modes are different. Using only one differential probe to test cannot meet the DUT working requirements. For the case of multiple data lanes, each lane can be tested separately.

The core of the test system is the D9020DPHC MIPI conformance test software platform. This software uses a graphical interface to guide users to complete the setting and connection of test parameters, and automatically completes signal quality testing and test report generation. It is very user-friendly and can greatly improve test efficiency.

1) Data LP-TX signal: ULPS sequence, etc., 50pF, lane0~lane4, DUT is usually CSI-2/DSI Master

2) Clock LP-TX: ULPS sequence, 50pF, Clock lane, DUT is usually CSI-2/DSI Master

3) Data HS-TX: HS Burst sequence (including LP exit/entry sequence), DUT is CSI-2/DSI Master, Lane0/1(ZID=100), Lane2/3(ZID:125/80)(HS-Entry test item), Lane0/1/2/3(ZID:100-125-80)(HS-TX Diff Voltage\Single-Ended High Voltage\Static Common-Mode Voltage&Mismatch\tR\tF), Lane0/1/2/3(ZID:100)(HS-TX Dynamic Common-Level Variations\HS Exit)

4) Clock HS-TX: HS Burst sequence (including LP exit/entry sequence), DUT is CSI-2/DSI Master, Clock (ZID: 100) (HS Entry\Common-Level Variations\HS Exit\HS Clock\SSC\Period Jitter), Clock (ZID: 80/125/100) (HS-TX Diff Voltage\tR\tF)

5) Clock/data timing requirements: HS Burst sequence (including LP exit/entry sequence), DUT is CSI-2/DSI Master/, ZID=100

6) Low power initialization sequence/ultra low power sequence/BTA requirements: Init/ULPS/BTA sequence, DUT is CSI-2/DSI Master&Device, 50pF

1) The VOH/VOL level test of the data signal LP-TX requires that the DUT data lanes 0~lane3 are connected to the 50pF capacitor load board for testing, and the DUT needs to generate a ULPS sequence. How to generate the sequence and what are the characteristics of the sequence are as follows. The DUT needs to work in LP-Escape Mode and enable the ULPS command ('00011110'). This mode is an asynchronous mode and uses Space-one-hot encoding. The clock signal of the other end is obtained through EXOR (Dp, Dn).

Figure: LP sequence of Escape mode

2) The high-speed data signal HS-TX differential voltage VOD(0) and VOD(1) are very important, and are related to the level standard of the measurement time parameter. Here, a pulse-based measurement method is selected and an average data processing algorithm is used. The HS sequence does not use the commonly used encoding method to achieve DC balance. In order to ensure measurement consistency, repeatability and easy acquisition of data content, two reference code types ('011111'/'100000') are selected as the data source to be aligned first and then averaged. This type of continuous 1 and continuous 0 is relatively typical in the content, and the capacitance effect and impedance adaptation effect can also be considered. During the test, consider measuring the clock and data at the same time, and the probe needs to be deskewed. To ensure accurate voltage measurement, the oscilloscope needs to meet the instrument calibration requirements. If it is a chip test, then lanes 0~3 are required to traverse different loads of RTB (80/125/100).

Figure: VOD(1) measurement waveform

3) High-speed clock and data timing parameters Tskewcal-sync/Tskewcal. The DUT operating rate exceeds 1.5Gbps and needs to support clock/data deskew.

This requires the DUT to generate an HS Burst Sequence, which includes LP-11/LP-01/LP-00/HS-0/synchronization code/calibration code/HS-TRAIL/HS-EXIT. The specific sequence waveform is as follows, where the synchronization code requires 16 consecutive 1s and the calibration code requires 4096 UI (alternating 0/1).

Figure: HS-TX SkewCal synchronization and calibration sequence

The following shows the measurement of time parameters for the sequence (rate about 2 Gbps) using an oscilloscope, where Tskewcal-sync obviously does not meet the typical time requirement of 16 ones, and Tskewcal obviously does not meet the typical time requirement of 4096 UIs.

Figure: HS-TX Tskewcal-sync measurement

Figure: HS-TX Tskewcal measurement

4) Chip testing has special test boards TVB and RTB to assist users in conformance according to standards. If it is a mobile terminal product, the measurement will be relatively complicated, and there will be problems such as small space, complex electromagnetic environment, and load parameters that are different from the standard. The measurement parameters and results can be used as a reference, and comprehensive measurement is very challenging.

The Rx test is completed based on a high-speed arbitrary waveform generator with automated test software. M8190/95A generates a specific waveform signal to simulate the Tx signal of MIPI D-PHY. After the signal is calibrated by an oscilloscope, it is input into the Rx of the DUT and the test is completed in the DUT. The test results can be obtained by reading the Error Counter of the DUT or reading the internal data of the DUT through the PPI interface or observing the image information, etc., especially for LP-RX, which depends on the capability of the DUT. The system test block diagram is as follows:

Figure: MIPI D-PHY Rx test block diagram

As mentioned above, since MIPI D-PHY signals include high-speed HS and low-power LP modes, with different signal amplitudes, data rates and formats, the Rx test modes of HS and LP need to switch seamlessly between different signal levels, data rates and formats. MIPI's D-PHY CTS (Conformance Test Suite) defines a series of different signal settings and calibration specifications. The M8085DC1A can complete the above calibration, signal generation and testing process in a self-service manner, allowing users to complete quick settings and tests without in-depth study of the CTS specification, which can greatly save learning cycles and testing time.

M8085A software can support debug and conformance tests. Support LP-RX voltage/timing Involving input voltage high and low, hysteresis, minimum pulse width response, interference tolerance, and competition monitoring threshold; LP-Rx behavior Requirements involve initialization time, wake-up time, invalid/termination sequence, Escape Mode sequence that ignores Post-Trigger-Command Extra bits commands, and Escape Mode sequence that does not support commands; HS-RX voltage/setup-hold time Requirements involve common-mode voltage tolerance, differential input high-level threshold, single-ended input high-level/low-level threshold, sinusoidal common-mode interference tolerance, setup-hold time & jitter tolerance; HS-RX time parameter Requirements, etc. The above test items are usually implemented using calibrated voltage, timing and other parameters to implement the test sequence HS or LP given to the DUT, and the judgment standard is to observe whether the DUT has a reception error (it can be whether the image is normal or whether the data is correct).

Figure: M8085A can edit and generate HS Burst, etc.

Data series in various formats

Figure: M8085A can generate CSI/DSI format frames

Figure: M8085A can generate signal level/jitter/interference/

Channel delay/time parameter/ISI/delay and other adjustable sequences

Due to the high complexity of the MIPI technology protocol and the high integration of the circuit board, there are many points that need to be paid attention to in actual testing. We have summarized several issues that need to be paid attention to in daily testing, hoping to help you avoid some detours in actual testing and improve efficiency.

01. MIPI D-PHY signal sequencing projects are numerous and complex

MIPI technology is mainly used in mobile devices. The board has high integration and small welding points. Welding is also a major problem in D-PHY testing, which requires a high level of engineering. When the welding points are inaccurate or the leads are too long, the signal will be too poor or even no signal will come out, resulting in the inability to perform the test. As shown in Figure 1 below, the signal point on the board is very small. The TX test of MIPI D-PHY requires the simultaneous access of 4 differential probes (1 pair of Data and 1 pair of Clock), with the positive pole of the front end connected to the signal and the negative pole to the ground; in a small space, as many test signals as possible are drawn out, which also puts high demands on the volume of the probe front end; here it is recommended to use the N5425B series probe front end with the 116xB series probe amplifier to provide good signal detection quality while keeping the probe small. Figure 2 below is a schematic diagram and a physical picture of the Tx test link.

Figure 1: MIPI measurement probe welding connection diagram

Figure 2: Schematic diagram of four 1169B probes connected to a 25G bandwidth oscilloscope

N5425B probe head

3. Selection of fixture for Tx test

In some high-speed serial technologies that utilize static state (such as PCI Express, SATA, etc.), the test equipment input port is usually used as the reference terminal load for measurement to complete the 100-ohm differential reference termination environment. However, because MIPI D-PHY technology utilizes a dynamic, switchable resistor termination at the receiver (power saving function), it is not possible to use the test equipment, that is, the oscilloscope, as the reference terminal. This switchable 100-ohm differential reference resistor termination is enabled in the high-speed (HS) operation mode and disabled in the low-power (LP) mode (open termination environment).

A common approach to performing MIPI D-PHY test measurements is to use a table of selected tests (high-speed mode or low-power mode testing) using a measurement fixture that can handle the various required termination loads, making the choice of fixture critical when doing Tx testing.

Generally speaking, there are two types of test fixtures available, one that can handle the required automatic switching of terminal loads and the other that only supports one terminal load at a time. Users need to choose between two different fixture adapters according to their needs during actual testing.

4. Calibrate channel probe delay

MIPI bus is mainly used in smart phones and mobile devices, so the interference of MIPI signal on RF signal is very important. Generally speaking, EMI is caused by common mode noise, and the specification has strict requirements on common mode noise. For example, the D-PHY v2.1 standard requires that the dynamic common mode noise above 450MHz should be less than 15mVrms. To meet this indicator, in addition to optimizing the design, it is also necessary to pay attention to the background noise of the oscilloscope itself and when using the probe, the measurement noise should be as small as possible under the condition of small vertical scale; in order to obtain accurate common mode noise parameters, the channel probe delay needs to be calibrated to reduce the common mode parameters introduced by channel delay.

5. LP and HS test network

C/D-PHY uses a mechanism that combines LP and HS. It is necessary to pay attention to the differences in test networking. For the eye diagram test of HS signals, such as the three-phase encoding of C-PHY, clock recovery is relatively special and requires the use of continuous HS code patterns for testing. In chip testing, it is necessary to directly connect to the oscilloscope via a coaxial cable to improve the measurement signal-to-noise ratio and eye diagram margin.

6. Calibrate the I-mode level to obtain accurate amplitude parameters

How to ensure the accuracy of absolute amplitude and common mode of HS signal in MIPI chip test? In C/D-PHY, since the signal itself has a common mode point, the parameters of HS signal such as eye diagram and transition time need to be directly connected to the oscilloscope through a coaxial cable for testing. Generally speaking, the oscilloscope has a 50ohm to ground structure. If it is measured directly in the oscilloscope, the common mode point level will be reduced. In order to ensure accurate common mode level and absolute amplitude, the N7010A termination adapter is required. In the C/D-PHY test software, the common mode level is calibrated through the N7010A calibration to obtain accurate amplitude parameters.

7. Synchronize AWG in Rx test to generate higher rate

In Rx testing, due to the multi-level characteristics of the signal and the need to measure parameters such as eSpike, in order to meet future higher-rate standards such as D-PHY v3.0, the test needs to use a high-performance AWG to synchronize two AWGs to generate C-PHY or D-PHY signals with a 10G symbol rate.

About ICC

Shanghai Integrated Circuit Technology and Industry Promotion Center (ICC) was established in February 2000. It is a national integrated circuit design industrialization base authorized by the Ministry of Science and Technology and a national "Core Fire" plan dual innovation platform authorized by the Ministry of Industry and Information Technology. It is committed to building a professional technical service platform for integrated circuit design, and promoting the high-quality development of my country's integrated circuit industry through professional technical services such as tape-out, EDA/IP resources, inspection and testing, and talent training. The ICC testing laboratory is a laboratory accredited by the China National Accreditation Service for Conformity Assessment (CNAS), providing the industry with professional testing services such as RFID and Internet of Things, high-speed signal integrity, and automotive Ethernet.