Features
•
High Performance, Low Power AVR
®
8-Bit Microcontroller
•
Advanced RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
Non-volatile Program and Data Memories
– 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny25/45/85)
Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes In-System Programmable EEPROM (ATtiny25/45/85)
Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes Internal SRAM (ATtiny25/45/85)
– Programming Lock for Self-Programming Flash Program and EEPROM Data
Security
Peripheral Features
– 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 8-bit High Speed Timer/Counter with Separate Prescaler
2 High Frequency PWM Outputs with Separate Output Compare Registers
Programmable Dead Time Generator
– Universal Serial Interface with Start Condition Detector
– 10-bit ADC
4 Single Ended Channels
2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
I/O and Packages
– Six Programmable I/O Lines
– 8-pin PDIP and 8-pin SOIC
Operating Voltage
– 1.8 - 5.5V for ATtiny25/45/85V
– 2.7 - 5.5V for ATtiny25/45/85
Speed Grade
– ATtiny25/45/85V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny25/45/85: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
Industrial Temperature Range
Low Power Consumption
– Active Mode:
1 MHz, 1.8V: 450µA
– Power-down Mode:
0.1µA at 1.8V
•
•
8-bit
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
ATtiny25/V
ATtiny45/V
ATtiny85/V
Preliminary
Summary
•
•
•
•
•
•
2586AS–AVR–02/05
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.
1. Pin Configurations
Figure 1-1.
Pinout ATtiny25/45/85
PDIP/SOIC
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/XTAL1/OC1B/ADC3) PB3
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
GND
1
2
3
4
8
7
6
5
VCC
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)
1.1
Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers
manufactured on the same process technology. Min and Max values will be available after the device is characterized.
2
ATtiny25/45/85
2586AS–AVR–02/05
ATtiny25/45/85
2. Overview
The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1.
Block Diagram
8-BIT DATABUS
CALIBRATED
INTERNAL
OSCILLATOR
PROGRAM
COUNTER
VCC
PROGRAM
FLASH
STACK
POINTER
WATCHDOG
TIMER
MCU CONTROL
REGISTER
TIMING AND
CONTROL
SRAM
MCU STATUS
REGISTER
GND
INSTRUCTION
REGISTER
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
DECODER
X
Y
Z
TIMER/
COUNTER0
TIMER/
COUNTER1
UNIVERSAL
SERIAL
INTERFACE
CONTROL
LINES
ALU
STATUS
REGISTER
INTERRUPT
UNIT
PROGRAMMING
LOGIC
DATA
EEPROM
OSCILLATORS
DATA REGISTER
PORT B
DATA DIR.
REG.PORT B
ADC /
ANALOG COMPARATOR
PORT B DRIVERS
RESET
PB0-PB5
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
3
2586AS–AVR–02/05
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATtiny25/45/85 provides the following features: 2/4/8K byte of In-System Programmable
Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32
general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high
speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel,
10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software select-
able power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The
Power-down mode saves the register contents, disabling all chip functions until the next Inter-
rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules
except ADC, to minimize switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,
and Evaluation kits.
2.2
2.2.1
Pin Descriptions
VCC
Supply voltage.
2.2.2
GND
Ground.
2.2.3
Port B (PB5..PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny25/45/85 as listed on
page 60.
On the ATtiny25 device the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged
in the ATtiny15 compatibility mode for supporting the backward compatibility with ATtiny15.
2.2.4
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in
Table 8-1 on page
37.
Shorter pulses are not guaranteed to generate a reset.
4
ATtiny25/45/85
2586AS–AVR–02/05
ATtiny25/45/85
3. Register Summary
Address
0x3F
0x3E
0x3D
0x3C
0x3B
0x3A
0x39
0x38
0x37
0x36
0x35
0x34
0x33
0x32
0x31
0x30
0x2F
0x2E
0x2D
0x2C
0x2B
0x2A
0x29
0x28
0x27
0x26
0x25
0x24
0x23
0x22
0x21
0x20
0x1F
0x1E
0x1D
0x1C
0x1B
0x1A
0x19
0x18
0x17
0x16
0x15
0x14
0x13
0x12
0x11
0x10
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Name
SREG
SPH
SPL
Reserved
GIMSK
GIFR
TIMSK
TIFR
SPMCSR
Reserved
MCUCR
MCUSR
TCCR0B
TCNT0
OSCCAL
TCCR1
TCNT1
OCR1A
OCR1C
GTCCR
OCR1B
TCCR0A
OCR0A
OCR0B
PLLCSR
CLKPR
DT1A
DT1B
DTPS1
DWDR
WDTCR
PRR
EEARH
EEARL
EEDR
EECR
Reserved
Reserved
Reserved
PORTB
DDRB
PINB
PCMSK
DIDR0
GPIOR2
GPIOR1
GPIOR0
USIBR
USIDR
USISR
USICR
Reserved
Reserved
Reserved
Reserved
ACSR
ADMUX
ADCSRA
ADCH
ADCL
ADCSRB
Reserved
Reserved
Reserved
Bit 7
I
–
SP7
–
–
–
–
–
–
–
FOC0A
Bit 6
T
–
SP6
INT0
INTF0
OCIE1A
OCF1A
–
PUD
–
FOC0B
Bit 5
H
–
SP5
PCIE
PCIF
OCIE1B
OCF1B
–
SE
–
–
Bit 4
S
–
SP4
–
–
–
OCIE0A
OCF0A
CTPB
–
SM1
–
–
Bit 3
V
–
SP3
–
–
OCIE0B
OCF0B
RFLB
SM0
WDRF
WGM02
Bit 2
N
–
SP2
–
–
TOIE1
TOV1
PGWRT
–
BORF
CS02
Bit 1
Z
–
SP1
–
–
TOIE0
TOV0
PGERS
ISC01
EXTRF
CS01
Bit 0
C
SP8
SP0
–
–
–
–
SPMEN
ISC00
PORF
CS00
Page
page 7
page 10
page 10
page 49
page 50
page 81
page 81
page 146
page 32, page 60, page 49
page 40,
page 79
page 80
page 27
Timer/Counter0
Oscillator Calibration Register
CTC1
PWM1A
COM1A1
COM1A0
CS13
CS12
CS11
CS10
Timer/Counter1
Timer/Counter1 Output Compare Register A
Timer/Counter1 Output Compare Register C
TSM
COM0A1
PWM1B
COM0A0
COM1B1
COM0B1
COM1B0
COM0B0
FOC1B
–
FOC1A
PSR1
WGM01
PSR0
WGM00
Timer/Counter1 Output Compare Register B
Timer/Counter0 – Output Compare Register A
Timer/Counter0 – Output Compare Register B
SM
CLKPCE
DT1AH3
DT1BH3
-
WDTIF
–
EEAR7
–
EEAR6
–
EEAR5
EEPM1
EEAR4
EEPM0
–
–
–
–
–
–
–
–
–
–
–
–
–
PORTB5
DDB5
PINB5
PCINT5
ADC0D
PORTB4
DDB4
PINB4
PCINT4
ADC2D
PORTB3
DDB3
PINB3
PCINT3
ADC3D
PORTB2
DDB2
PINB2
PCINT2
ADC1D
PORTB1
DDB1
PINB1
PCINT1
EIN1D
PORTB0
DDB0
PINB0
PCINT0
AIN0D
–
–
DT1AH2
DT1BH2
-
WDTIE
–
–
DT1AH1
DT1BH1
-
WDP3
–
–
DT1AH0
DT1BH0
-
DWDR[7:0]
WDCE
WDE
PRTIM1
EEAR3
EERIE
WDP2
PRTIM0
EEAR2
EEMWE
WDP1
PRUSI
EEAR1
EEWE
WDP0
PRADC
EEAR8
EEAR0
EERE
EEPROM Data Register
–
CLKPS3
DT1AL3
DT1BL3
-
PCKE
CLKPS2
DT1AL2
DT1BL2
-
PLLE
CLKPS1
DT1AL1
DT1BL1
DTPS11
PLOCK
CLKPS0
DT1AL0
DT1BL0
DTPS10
page 88, page 100
page 90, page 101
page 90, page 102
page 91, page 102
page 84, page 89, page
page 91
page 76
page 80
page 80
page 93, page 103
page 30
page 108
page 109
page 108
page 143
page 42
page 33
page 16
page 16
page 16
page 17
page 64
page 64
page 64
page 51
page 124, page 141
General Purpose I/O Register 2
General Purpose I/O Register 1
General Purpose I/O Register 0
USI Buffer Register
USI Data Register
USICIF
USISIE
USIOIF
USIOIE
USIPF
USIWM1
USIDC
USIWM0
–
–
–
–
ACD
REFS1
ADEN
ACBG
REFS0
ADSC
ACO
ADLAR
ADATE
ACI
REFS2
ADIF
ACIE
MUX3
ADIE
–
MUX2
ADPS2
ACIS1
MUX1
ADPS1
ACIS0
MUX0
ADPS0
page 122
page 137
page 138
page 140
page 140
ADTS2
ADTS1
ADTS0
page 122, page 140
USICNT3
USICS1
USICNT2
USICS0
USICNT1
USICLK
USICNT0
USITC
page 118
page 117
page 118
page 119
ADC Data Register High Byte
ADC Data Register Low Byte
BIN
ACME
IPR
–
–
–
–
–
5
2586AS–AVR–02/05