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From sand to chips: How processors are made

Latest update time:2021-09-01 15:03
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It can be said that the central processing unit (CPU) is the power source of the rapid operation of modern society. Microchips can be found in any electronic device, but some people are dismissive and think that the processor has no technical content and is just a pile of sand. Is it true? Intel today released a large amount of graphic materials, showing in detail the whole process from sand to chip. It is easy to tell at a glance.

Simply put, the manufacturing process of a processor can be roughly divided into many steps, including sand raw materials (quartz), silicon ingots, wafers, photolithography (lithography), etching, ion implantation, metal deposition, metal layers, interconnection, wafer testing and cutting, core packaging, grade testing, packaging and listing , and each step contains more detailed processes.

Below is a combination of pictures and text, take a look step by step:

Sand : Silicon is the second most abundant element in the Earth's crust, and deoxygenated sand (especially quartz) contains up to 25% silicon in the form of silicon dioxide (SiO2) , which is the basis of the semiconductor manufacturing industry.

Silicon smelting : 12-inch/300mm wafer level, the same below. Silicon of semiconductor manufacturing quality is obtained through multiple purification steps. The scientific name is Electronic Grade Silicon (EGS) . On average, there is only one impurity atom in every million silicon atoms . This figure shows how large crystals are obtained through silicon purification and smelting, and the final product is a silicon ingot.

Single crystal silicon ingot : It is basically cylindrical in shape, weighs about 100 kg , and has a silicon purity of 99.9999% .


Group photo of the first stage


Silicon ingot cutting : Cutting into circular individual silicon slices horizontally, which is what we often call wafers. By the way, now you know why wafers are all round, right?

Wafer : After being cut, the wafer becomes almost flawless after being polished, and the surface can even be used as a mirror. In fact, Intel does not produce this kind of wafer itself, but directly purchases finished products from third-party semiconductor companies, and then further processes them using its own production lines , such as the current mainstream 45nm HKMG (high-k metal gate). It is worth mentioning that the wafer size used by Intel when it was first founded was only 2 inches/50 mm.


Group photo of the second stage


Photoresist : The blue part in the picture is the photoresist liquid poured on the wafer during the rotation process, similar to the one used to make traditional film. The rotation of the wafer allows the photoresist to be spread very thinly and very flat.

Photolithography : The photoresist layer is then exposed to ultraviolet light (UV) through a mask , becoming soluble, and the chemical reaction that occurs during this period is similar to the change in the film when the shutter of a mechanical camera is pressed. The mask is printed with a pre-designed circuit pattern, and ultraviolet light shines through it onto the photoresist layer, forming each layer of the circuit pattern of the microprocessor. Generally speaking, the circuit pattern obtained on the wafer is one-fourth of the pattern on the mask.

Photolithography : This is where we get to the 50-200 nanometer transistor level. Hundreds of processors can be cut from a wafer, but from here we zoom out to one of them and show how to make components like transistors. Transistors are like switches that control the direction of current flow. Today's transistors are so small that about 30 million of them can fit on the head of a pin.


Group photo of the third stage


Dissolving photoresist : During the photolithography process, the photoresist exposed to ultraviolet light is dissolved, and the pattern left after removal is consistent with that on the mask.

Etching : Chemicals are used to dissolve away exposed portions of the wafer, while the remaining photoresist protects the portions that should not be etched.

Removing photoresist : After etching is completed, the photoresist's mission is accomplished. After it is completely removed, the designed circuit pattern can be seen.


Group photo of the fourth stage


Photoresist : Pour photoresist (blue part) again, then perform photolithography, and wash away the exposed part. The remaining photoresist is still used to protect the part of the material that will not be ion implanted.

Ion implantation : In a vacuum system, accelerated ions of atoms to be doped are used to irradiate (implant) solid materials, thereby forming a special implantation layer in the implanted area and changing the conductivity of silicon in these areas. After being accelerated by an electric field, the speed of the injected ion flow can exceed 300,000 kilometers per hour .

Removing the photoresist : After the ion implantation is completed, the photoresist is also removed, and the implanted area (green part) is also doped with different atoms. Note that the green color at this time is different from before.


Group photo of the fifth stage


Transistor ready : At this point, the transistor is almost complete. Three holes are etched in the insulating material (magenta) and filled with copper to interconnect with other transistors.

Electroplating : A layer of copper sulfate is electroplated on the wafer to deposit copper ions on the transistor. The copper ions will move from the positive electrode (anode) to the negative electrode (cathode).

Copper layer : After electroplating is completed, copper ions are deposited on the surface of the wafer to form a thin copper layer.


Group photo of the sixth stage


Polishing : Polish off the excess copper, that is, polish the surface of the wafer.

Metal layer : transistor level, a combination of six transistors, about 500 nanometers. Composite interconnect metal layers are formed between different transistors, and the specific layout depends on the different functionalities required by the corresponding processor. The surface of the chip looks extremely smooth, but in fact it may contain more than 20 complex circuits. When zoomed in, you can see an extremely complex circuit network, like a futuristic multi-layer highway system.


Group photo of the seventh stage


Wafer testing : core level, approximately 10 mm/0.5 in. Pictured is a portion of a wafer undergoing its first functional test, using a reference circuit pattern to compare each die.

Wafer slicing : Wafer level, 300 mm/12 inches. Cut the wafer into blocks, each of which is a processor core (die).

Discarding defective cores : Wafer level. Defective cores found during testing are discarded, leaving intact cores ready for the next step.


Group photo of the eighth stage

Single core : Core level. A single core cut from a wafer, shown here is a Core i7 core.

Package : Package level, 20 mm/1 inch. Substrate (base), core, heat sink Stacked together, they form the processor we see. The substrate (green) is equivalent to a base and provides an electrical and mechanical interface for the processor core to facilitate interaction with other parts of the PC system. The heat sink (silver) is responsible for the heat dissipation of the core.

Processor : Now you have a complete processor (here is a Core i7). This most complex product made in the cleanest room in the world actually goes through hundreds of steps, only some of the key steps are shown here.


Group photo at the ninth stage


Level test : The last test can identify the key characteristics of each processor, such as maximum frequency, power consumption, heat generation, etc., and determine the level of the processor, such as whether it is suitable for making the highest-end Core i7-975 Extreme or the low-end model Core i7-920.

Packing : Processors of the same level are shipped together based on the grade test results.

Retail packaging : Processors that have been manufactured and tested are either delivered in batches to OEMs or placed in packaging to enter the retail market. Here we take the Core i7 as an example.


Group photo of the tenth stage


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