Led by 10nm, new technology strategy will lead Intel's comprehensive counterattack

On September 19, 2017, Intel held an Intel Advanced Manufacturing Day event in Beijing titled "Leading without Boundaries". According to Mr. Yang Xu, Intel 's Global Vice President and President of China, this was the second time Intel held such an event and the first time it was held in China.

At the conference, in addition to introducing some of the company's investment status in China, Intel experts also delivered a rich speech on the future development of Moore's Law, the specification of node naming, the development of 10nm and the future development of wafer foundry business. The following is a detailed report from Semiconductor Industry Observer:

Since the launch of 14nm technology a few years ago, there has been no progress on Intel's new node technology for a long time, only a few feature and performance upgrades on 14nm. On the contrary, competitors have seen more progress on 10nm and 7nm, and even several 10nm chips have been seen on the market. Many people are discussing Intel 's 10nm delay information, and even believe that Intel has fallen behind its competitors in process technology. Every time Intel is asked about related questions, it will remain silent.

Today, Intel finally brought the latest 10nm technology.

Intel Stacy J. Smith, executive vice president and president of manufacturing, operations and sales group, officially unveiled a 10nm silicon wafer on the podium.

According to Mark T. Bohr, Intel senior fellow and director of process architecture and integration of the Technology and Manufacturing Division, due to the application of new hyperscaling technology and the full use of multi-patterning technology, Ittel's new 10nm technology has achieved an unprecedented breakthrough. It is revealed that the new technology integrates more than 100 million transistors per square millimeter, which is a significant improvement compared to the 37.5 million of the previous generation 14nm.

As mentioned earlier, this is all achieved based on its new generation of ultra-miniaturized technology.

According to Mark, Intel 's 10nm technology uses the third-generation FinFET technology. Compared with the previous generation of products, the fin spacing of 10nm is reduced from 42nm to 34nm, which is 0.81 times that of the previous generation; the minimum metal spacing is also reduced from 52nm to 36nm, which is almost 50% lower than the previous generation; the cell height is also reduced from 399nm to 272nm; the gate spacing is also reduced from 70nm to 54nm. In addition, the virtual gate is reduced from two to one, and the gate contact is changed from standard to COAG. These points create the advanced performance of the 10nm chip.

First, let’s look at the improvements of the third-generation FinFET. According to Intel , compared with 14nm, the new generation 10nm process has a 25% increase in fin height, a 25% decrease in spacing, and a 45% reduction in power consumption.

There are also changes brought about by the change of the contacts on the active gate. This technology, called contact overactive gate, is a revolutionary innovation that can further reduce the chip area by 10%. According to Bai Peng, Intel 's global vice president and co-director of the logic technology development department: As shown in the figure below, if the contacts are moved up and superimposed on the fins, the gate segment where the original contacts are located can be removed, thus achieving the purpose of reducing the area.

Through continuous optimization, Intel 's 10nm transistors have also achieved significant improvements in performance and power consumption.

When compared with competitors' "same-generation" technologies, Intel said: As always, Intel's new technology is one generation ahead of its competitors, which is three years.

For example, in terms of performance and power consumption, Intel 's active power is 20% and 30% ahead of its competitors.

Intel is also ahead of its competitors in terms of logic transistor density . This is also a full generation ahead.

The improvement of SRAM also effectively improves the miniaturization of products. This is the advantage that Intel has always maintained.

In terms of various data comparisons, Intel also basically beats its competitors.

With the support of these technologies, Intel's 10nm chip can be as small as 7.6mm², with improved density and performance. This reduces the cost of each transistor and meets the requirements of Moore's Law.

Intel said that their 10nm technology will be applied to clients, servers and other types of equipment. The new technology will be officially mass-produced in the second half of 2017.

In addition, Intel also emphasized that since the current process advancement cycle is longer than before, in order to better meet customer needs, Intel will launch several different processes at each generation node to meet the performance upgrade needs of products. For example, at 10nm, there are 1nm+ and 10nm++, and the performance of each generation here will be significantly improved compared to the previous one.

In addition to disclosing the 10nm technology, Intel also announced the launch of the world's first FinFET technology for low-power IoT and mobile products - 22FFL at this process conference. Intel said that relying on their deep technical foundation, this new process will bring their customers a higher performance/price ratio.

Looking back at Intel ’s process development history, their FinFET process debuted at 22nm. Intel’s new development at this node, which is of great significance to FinFET, reflects Intel’s high hopes for this process technology.

Because the new process uses advanced FinFET transistors, compared with the traditional 22nm general technology, the leakage current of the new 22nmFFL process can be reduced by up to one hundred times, and the total leakage of low-leakage transistors is even only one-five hundredth of that of the general 22nm technology; on this process, it even achieves the same driving current as the 14nm transistor; in addition, based on 22nm, it provides simplified interconnection technology and design principles, a higher level of design automation, and support for complete shooter design. The new process is very competitive compared with its competitors.

Intel said that compared with the 28nm/22nm planar technology of the same industry, it has a higher area miniaturization and great cost advantages. With the support of the industry chain ecology, in the foreseeable future, this will be a big killer for Intel in the wafer foundry market. Intel also said that this technology has now withdrawn from the industry standard PDK1.0 and will be ready for production in the fourth quarter of 2017.

In addition to 22nm FFL, Intel also emphasized at the meeting that it will increase its investment in the foundry market and promote the further development of its foundry business.

Zane A. Ball, vice president of Intel's Technology and Manufacturing Division and co-general manager of foundry business, said that in the past few years, the top foundry market has been growing rapidly, coupled with the growth of semiconductor demand in China. Intel, seeing the huge opportunity, will seize the high-end foundry market through various combinations.

Zane said that Intel will combine the advantages of 22nm, 14nm, 10nm and 22FFL processes, plus jointly optimized design kits, silicon-verified IP and innovative packaging and testing capabilities, to provide foundry services for network infrastructure and mobile and connected devices.

He said that because Intel's transistor density is twice as high as other technologies, it can bring higher technology density to network infrastructure; in addition, their 56Gbps PAM4 SerDes is already in the trial stage, and 112Gbps SerDes is also in the development stage, which will bring higher-speed transmission to network facilities; in addition, through the embedded multi-chip interconnect bridge (EMIB) technology, heterogeneous chips can be integrated to achieve high density, high bandwidth and low cost, which will bring economical multi-chip integration to network infrastructure. The above three points will also become the basis for Intel to develop foundry business in this field.

We know that in the booming mobile chip market in the past few years, Intel missed a big opportunity due to subjective or considerable reasons. Although this brought Intel a short-term embarrassment, Intel , which has a deep process advantage , found a better way to enter the market, that is, foundry.

According to Zane, Intel's process can achieve faster time to market, higher energy consumption and smaller size in mobile and connected devices. It can achieve leading power consumption/performance ratio in mainstream products, and ultra-low leakage, low cost and easy design in the Internet of Things and entry-level mobile devices.

Since announcing its cooperation with ARM in 2016, Intel has completed the process from RTL to the first tape out in just over a dozen weeks. In August of this year, Intel even completed the test chip of ARM Cortex-A75 CPU core using Intel's 10nm process. It is worth mentioning that the transistor density of this chip is also far ahead of other competitors. It can be seen that the progress of cooperation with ARM will push Intel to go further in the ARM foundry market, and also start their competition for ARM's high-end chips.

As for the Internet of Things and entry-level mobile markets, they are the areas that Intel 22nmFFL focuses on. Some readers may be confused here. Intel is also attacking the Internet of Things here, and competitors are also using FD-SOI technology to attack the Internet of Things market. How will the competitive advantages between the two be chosen?

Mark told the Semiconductor Industry Observer reporter: "FD-SOI requires expensive substrates and complex tools, and these are not perfect, which is a big challenge for FD-SOI." He emphasized from beginning to end that 22FFL is the best choice for IoT design.

Intel also stated that it will bring 14nm and 22FFL FinFET technologies to the Chinese market.

We know that in the past foundry market, there were giants such as TSMC, Samsung and GlobalFoundries, as well as manufacturers such as Unigroup and Towerjazz. There are also countless domestic SMIC and a number of low-end process manufacturers. Intel chose this time to emphasize whether foundry will face competitive pressure and whether it can open up a market.

Yang Xu directly replied, "If the tiger doesn't show its power, you will think I'm a sick cat." The meaning of his answer was clear.

Regarding the high-end 10nm foundry, Bai Peng said that Intel 's senior technical accumulation is the basis, and the fabless companies that step into advanced processes need different suppliers, which can promote the development of Intel 's business. This is also the reason why Intel is optimistic about the foundry business.

In addition to revealing a series of new technologies, Intel also talked about its development and innovation in China at this year's manufacturing conference. Since entering China in 1985, Intel has maintained a substantial investment in China, especially since the 21st century, with faster investment and more diverse cooperation methods.

According to Intel, their total investment in mainland China has exceeded 13 billion US dollars, covering technology research, product development, chip manufacturing, packaging and testing, marketing, services and venture capital. Intel emphasized that these investments make Intel China the most complete layout outside the United States. Among them, the following are the most eye-catching:

In August 2003, Intel announced its investment in Chengdu to build a chip packaging and testing plant. In November 2016, high-end testing technology was officially put into production at Intel's Chengdu plant, making it the only high-end testing technology plant outside the United States, and fully realizing a major "innovation and transformation" that integrates chip packaging and testing, wafer pre-processing and high-end testing technologies.

Intel said that the Chengdu plant is one of Intel's largest chip packaging and testing centers in the world. By the end of 2016, it had produced 2.06 billion chipsets and mobile processors. It is also one of Intel's two largest wafer pre-processing plants in the world. In 2012, Intel's Western China Branch Center was also established in Chengdu Hi-tech Zone.

By 2007, Intel's Dalian factory was also laid. This is Intel's first wafer manufacturing plant in Asia. The initial total investment in the plant was US$2.5 billion, and it was officially put into production in 2010. But in 2015, Intel upgraded it and invested up to US$5.5 billion to upgrade this plant to a "non-volatile memory" manufacturing base. It has become one of Intel 's production centers using the most advanced technology of 300mm wafers in Intel's global manufacturing network for non-volatile memory product integrated circuits. The newly upgraded factory also helped Dalian become a leading city in the world in non-volatile memory manufacturing technology. The project was officially put into production in July 2016.

In May 2017, Intel released two new data center-level SSDs using 3D NAND at its Dalian plant. At the same time, the Dalian plant, which is a manufacturing base for "non-volatile memory", is being expanded to meet the growing market demand for 3D NAND. Today, Intel also launched the world's first Intel 64-layer 3D NAND SSD for data centers. This is also a product from Intel's Dalian plant.

In 2014, Intel announced an investment of RMB 9 billion in the holding company of Spreadtrum Communications and RDA Microelectronics under Tsinghua Unigroup to jointly develop system chips and promote the development of new computing software and hardware with independent intellectual property rights. In 2017, Intel and Spreadtrum launched the 8-core 64-bit LTE chip platforms SC9861G-IA and SC9853I, which use Intel's advanced 14nm FinFET process technology and built-in Intel Airmont processor architecture, targeting the global mid-to-high-end mobile market and improving users' intelligent experience. This is a major attempt by Intel to help local chip design companies improve.

In addition, in April 2015, Intel announced that it would work with Tsinghua University to promote the development of new computing hardware and software based on reconfigurable computing technology with independent intellectual property rights. In January 2016, Intel signed an agreement with Tsinghua University and Montage Technology, a subsidiary of China Electronics Information Industry Group, to jointly develop a new general-purpose processor that integrates reconfigurable computing and Intel x86 architecture technology to serve the Chinese market; in May 2017, Montage Technology, together with Tsinghua University and Intel, officially released the secure and controllable Jintai CPU hardware and software reference development platform for data center applications, and the project is scheduled to be commercially deployed in 2018.

The above cooperation is common and will continue to happen.

Yang Xu said that by 2020, China's data will reach 8ZB, which will be the world's largest market; by then, the ICT industry revenue from China will reach 530 billion US dollars; the IC market revenue will be as high as 139 billion US dollars. The Chinese market will definitely be a battleground for semiconductor companies in the future, and Intel will continue to invest in it.

Since Gordon Moore proposed Moore's Law in 1965, the integrated circuit industry has been developing in accordance with this commonly known economic law. However, as chip manufacturing processes advance to below 10nm, there has been more discussion about the future of Moore's Law and the development of the integrated circuit industry, and some even believe that Moore's Law will come to an end. When asked about their views on this issue, Intel executives said categorically: Moore's Law will continue to evolve and will continue to evolve.

Intel said that the increase in transistor density is the driving force behind Moore's Law, and the decrease in the average price of transistors brought about by the increase in density is also the driving force behind Moore's Law. Both of these have been happening all the time, so they firmly believe that Moore's Law will not fail. They also gave an example to illustrate:

According to Moore's Law, transistors are an important part of ensuring the continued evolution of Moore's Law. Intel has introduced ultra-miniaturization technology since 14nm, which will drive the continued shrinking of transistors.

This scaling will also give Intel a lower average transistor cost.

"Intel has been driving technological innovation and leading the development of Moore's Law," Mark T. Bohr told reporters.

From the introduction of strained silicon chips at 90nm in 2003 to the production of high-K metal gate chips in 2007, from the self-calibrated channel at 32nm to the introduction of FinFET at 22nm, Intel has always been leading the trend of industry technology, and in all of these technologies, Intel is three years ahead of its competitors, Mark emphasized.

Although Intel firmly believes that Moore's Law will not end, Mark told reporters: "It is true that we may reach the physical limit one day, but we can't see the end yet." Therefore, Intel is still working hard to continue to push Moore's Law forward.

They said that from a technical point of view, it is becoming increasingly difficult and expensive to implement new process nodes one by one. Just installing the equipment in an existing wafer fab will cost $7 billion. This also means that the semiconductor manufacturing industry will continue to consolidate, because fewer and fewer companies can afford the cost of advancing Moore's Law. But Intel makes its products lower in price and more powerful every year. Because in their view, the ability to advance Moore's Law is their core competitiveness.

But Mark said that while Intel was fully committed to promoting Moore's Law for the industry and increasing customer benefits, some competitors were too casual in naming nodes, which gave the industry an illusion that their technology was far ahead of the market.

But as mentioned before, Intel has twice the transistor density of its competitors at 10nm. The reason for this is that competitors have deviated from the node naming, which has caused bad effects. This requires the industry to have a standardized naming method.

They point out that if you want to standardize, there is a simple formula that multiplies the gate pitch (gate width plus the spacing between transistor gates) by the minimum metal pitch (interconnect line width plus line spacing), but this does not include logic cell design, which will affect the actual transistor density. Another formula - gate pitch multiplied by logic cell height - is a step in the right direction to correct the above shortcomings. However, neither formula fully takes into account some second-order design rules.

None of them are true measures of actual achieved transistor density, as none of them attempt to account for the different types of logic cells in the design library and these metrics quantify relative density relative to the previous generation. What the industry really needs is the absolute number of transistors in a given area (per square millimeter).

At the other extreme, a formula that simply divides a chip's total transistor count by its area is meaningless because a large number of design decisions affect it - factors such as cache size and performance targets can cause this value to change dramatically.

It is time to resurrect a once popular but once-out-of-favor calculation based on the transistor density of standard logic cells, with multiple weighted factors that determine a typical design. While there are many choices of standard cells in any design library, we can take a popular, very simple cell - the 2-input NAND cell (4 transistors), and a more complex, but also very common cell: the scan flip-flop (SFF). This allows us to derive the previously accepted formula for measuring transistor density.

Mark believes that under this formula, the industry can sort out the confusion of process node naming and focus on promoting Moore's Law. However, this formula was proposed by the industry, not Intel itself, Mark emphasized.

After getting these concepts and names, Mark continued to talk about Intel’s views on Moore’s Law and the future development of integrated circuits.

Mark pointed out that Intel believes that the process upgrade cycle will be longer in the future, but Intel will insist on using new technologies to promote Moore's Law. Intel officials have also invested in research on some new technologies. These include nanowire transistors, III-V transistors, 3D stacking, dense memory, dense interconnection, EUV patterning, neuron computing and spin electronics.

When asked about Intel 's views on More than Moore and Beyond CMOS, which the industry is paying attention to.

Mark told reporters that he believes that as the process continues to shrink, Beyond CMOS may become a good choice, but not now. Intel itself is also paying attention to and investing in these technologies.

As for EUV, which the industry is paying attention to, when asked about Intel's plan in this regard, Mark told reporters: If EUV is ready, Intel will definitely equip it without hesitation, there is no doubt about it. But from their point of view, the current EUV still has problems such as insufficient lithography speed and insufficient tool continuity time. In addition, the photolithography tools and mask directions also need to be matched. In the near future, they think it is not a good time to use EUV, but they keep a close eye on it.

From DRAM to processors, and then back to Flash; from traditional IDM to Fab foundry; from a PC processor supplier to a cloud computing platform supplier, Intel is constantly changing. So far, it has achieved good results. However, looking forward to the future, Intel will face equally severe challenges in these areas. However, with the support of these technologies and forward-looking layouts, we believe that Intel will sweep away the decadence of the previous mobile chip era and launch a comprehensive counterattack. (Text/Li Shoupeng)

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