How does Intel open the door to the future?

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There was a lot of buzz around AI and multi-chip heterogeneous design at this year’s DAC. The focus of many of the panels and presentations at the conference was on the promise of bringing 2.5/3D design and the chiplet ecosystem to the mainstream. AI is certainly a driver of this new style of design, but as you’ll see, the discussion extends beyond AI. This new style of design requires efforts from every part of the semiconductor ecosystem, and this focus was on display during DAC. There is a focal point where all of this work needs to come together to achieve commercialization. That focal point is the foundry, and there was a keynote at DAC on Tuesday morning that did a great job of explaining how to open the door to the future. Let’s explore how Intel’s Gary Patton demonstrated the path to the system foundry.

What is a System Fab and Why It Matters

Before I get into Gary's keynote, I want to address the obvious. I've been in the semiconductor industry for a long time. For many years, I thought of Intel as a technology giant that dominated the market, crushed the competition, and did things the Intel way.

When I hear "Intel," the first thing that comes to my mind isn't necessarily open, collaborative, ecosystem-centric, and service-oriented. But that's exactly what Dr. Gary Patton delivered during his keynote. Intel is clearly changing dramatically. With its Systems Foundry initiative, Intel is taking a leadership role in defining the future of semiconductor design and manufacturing. This role requires a new type of culture, and Gary is one of the Intel executives leading the charge. I had the opportunity to speak one-on-one with Gary at DAC, and I'll share some of his personal insights in a moment. But first, let's take a look at some of the information from his keynote.

Gary started with some eye-opening statistics. According to IDC, the world generates nearly 270,000 petabytes of data every day. That’s 270,000,000,000 gigabytes. Intel estimates that by 2030, 1 petaflop and 1 petabyte of data will be within 1 millisecond of the average user. Achieving these feats requires disruptive innovation—innovation that clearly goes beyond the Moore’s Law we’ve relied on for so long.

He also mentioned that AI, while driving a massive increase in data volumes and data processing needs, also poses a huge energy efficiency challenge. According to The New York Times and Google, AI may soon require the equivalent of a country’s electricity (about 100 terawatt-hours per year).

Gary pointed out that disruptive innovation is nothing new to our industry. Over the years, we have overcome the bipolar power limit, the gate oxide limit, and now the planar device limit. Overcoming the last limit requires a combination of chip and chipset implementation and package interconnect density and energy efficiency. Intel's goal is to be at the center of all these innovations, and this is what its Systems Foundry program is all about.

Thanks to its advanced packaging work, Intel is on track to achieve a 50x improvement in energy efficiency and a 10,000x improvement in interconnect density, as shown in the chart below.

Gary saw the full picture through Intel’s innovation. He presented the work of UCIe, a consortium of 135 companies. The stated goal of the consortium is to develop an open specification that defines the interconnect between chips within a package, enabling an open chip ecosystem and ubiquitous interconnect at the package level. Gary explained that the work of UCIe has enabled two orders of magnitude improvement in energy efficiency and three to four orders of magnitude improvement in bandwidth compared to the standard package in the lower left of the above figure. These packaging improvements also reduce latency by at least an order of magnitude compared to external interconnects such as PCIe, Ethernet, etc. This is important work that Intel’s foundry explicitly supports.

Gary then discussed the importance of system technology co-optimization, which is a broader and more ambitious version of design technology co-optimization. He explained that software and architecture, packaging and silicon are all part of this effort and must be holistic. He stated, "Progress at individual layers in the stack is necessary but not sufficient. The entire system must be co-optimized."

While much of Intel’s advanced process and packaging work is driving this effort, close collaboration with the entire IP, EDA, design services, and advanced system assembly and test ecosystem is also key to success. He detailed the many initiatives Intel foundries are undertaking with their ecosystem partners to build and certify next-generation design and manufacturing capabilities. He described regular meetings with all the major EDA vendors and showed a very detailed scorecard covering EDA certifications for all key Intel technologies. The breadth of this effort is truly impressive. Intel’s commitment to an open design flow will be further demonstrated later in this article.

Gary described Intel’s five-year investment to achieve system foundry capabilities. He reported that the company now has more than 100 2.5D designs in manufacturing. Design support, an open and collaborative attitude, a quality-first culture, strong customer support, and a certified methodology are all part of this investment, as shown in the figure below.

The chart above really hits the spot. This is a completely new and upgraded version of Intel. It retains Intel's technological advantages, but adds all the elements of a leading, world-class foundry to create a system foundry. Next, let's get to know the host of the keynote.

I had the opportunity to speak with Gary privately after his keynote at DAC. Gary is one of many “outsiders” that Intel has hired over the past few years – the five-year investment summarized above. I think Gary’s entire career has prepared him for his current role at Intel. After earning his PhD in Electrical Engineering from Stanford University, he spent over 25 years at IBM in various leadership roles across research, microelectronics, and various corporate initiatives and product lines. During this time, he honed his skills in product/technology development as well as ecosystem collaboration.

He then worked at Globalfoundries for 4.5 years as CTO and SVP of Global R&D and Design Enablement. He has now been at Intel for 4.5 years as Corporate Vice President and General Manager of Foundry Design Enablement. He is one of many recent Intel hires who brings a wealth of industry experience to the company.

Gary explained that he has always had great respect for what Intel has accomplished. He came to the company not to “fix” anything, but to take this great company to the next level. And that seems to be working out well. He considers the past 4.5 years to be the best of his career. That means a lot when you consider all that he has accomplished.

Gary spoke about the company-wide transformation Intel is making to meet the broader challenges and opportunities ahead. The tone from the top is an important part of this, and Pat Gelsinger is just the right person to convey that message. It was a pleasure to talk to Gary. He is articulate, approachable, and a very effective leader. His last words really stood out to me. He explained that he had learned many lessons from his previous experiences that he brought with him to Intel. One of the key lessons was, "If you're in the foundry business, your customers make you better."

Proof of Intel's Commitment to Open Design Flow

Day one of DAC is further evidence of the continued growth of the Intel ecosystem and its commitment to creating a broad reference flow. Intel ecosystem partners made the following announcements to enable access to Intel’s EMIB technology:

Ansys is collaborating with Intel Foundry to perform signoff verification of thermal integrity, power integrity and mechanical reliability of Intel EMIB technology, covering advanced silicon process nodes and various heterogeneous packaging platforms.

Cadence announced the availability of a complete EMIB 2.5D packaging flow, digital and custom/analog flows for Intel 18A, and design IP for Intel 18A.

Siemens announced that it is providing the EMIB reference flow to Intel foundry customers. In addition, Siemens also announced that the Solido™ simulation suite has been certified for Intel 16, Intel 3, and Intel 18A node custom IC verification.

Synopsys announces AI-driven multi-chip reference flow for Intel® EMIB advanced packaging technology to accelerate development of multi-chip designs.

“Today’s news demonstrates how Intel Foundry continues to combine the best of Intel with the best of our ecosystem to help our customers realize their AI system ambitions,” said Suk Lee, vice president of foundry ecosystem development at Intel.

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