ASML’s dilemma: High NA is too difficult

In recent years, the “next big thing” in lithography has been high-numerical aperture extreme ultraviolet (IE high-NA EUV), the next revolutionary step in the development of ASML’s lithography tool technology. High-NA is advertised as reducing process complexity and being able to scale beyond 2nm. In ASML's view, this will reduce complexity and cost.

Our lithography modeling shows that despite the reduced complexity, high numerical aperture EUV single patterning costs significantly more than dual patterning using existing low numerical aperture machines, and this applies to including 1.4nm/14A, coming soon technology nodes. In addition, multi-pattern low NA EUV enables finer pitch features than High NA.

ASML has many lofty goals, such as reaching annual shipments of 600 DUV and 90 EUV tools by 2025, but in our opinion their most lofty goal - shipping 20 high numerical aperture tools annually by 2028 Plans for EUV tools – difficult to achieve. High numerical aperture lithography introduces many new technical challenges that need to be solved and industrialized, but the most difficult ones are economic. Before we go into detail about cost and other key issues below, let's briefly mention what's happening in EUV and DRAM.

Samsung has been at the forefront of DRAM technology for much of the past two decades, giving it clear advantages in density, performance and cost scaling over rivals such as Micron and SK Hynix. That all changed with the advent of D1Z generation DRAM, as Samsung adopted EUV too quickly (among other issues) and suffered. Due to various cost and yield issues, they are unable to effectively promote new EUV-based DRAM process technology. Thanks to Samsung's mistakes, SK Hynix and especially Micron were able to lead in terms of density and cost structure. Today, although Samsung has fully adopted EUV, it still lags behind in the density and performance race. Micron, despite using DUV, still has the densest DRAM in the world by a considerable margin.

But let's be clear that the economic challenges faced by High NA are much more severe than those faced by Low NA, although the technical challenges may be smaller.

We don’t need to revisit the details of EUV lithography, but let’s review a brief history of the decisions that led to the high NA that exists today.

To continue shrinking logic and memory nodes, lithography tools (scanners) must be able to print smaller features. At the outset of high numerical aperture development, chipmakers and ASML faced difficult architectural decisions on how to achieve this goal. Fundamentally, there are 2 main knobs in scanner design for imaging smaller features: 1) Reduce the wavelength of the light source 2) Increase the size of the lens (or more accurately, the numerical aperture or NA of the lens). This choice is formulated as the first Rayleigh criterion. This rule is so common that ASML even prints it on T-shirts.

The industry has chosen to pursue larger projection lenses for a number of valid technical reasons. Unfortunately, lens size cannot be made larger without causing other problems, primarily due to limitations of EUV photomask technology as it relates to chief ray angle. This forces further compromises in high numerical aperture architectures.

ASML and its partners face a series of bad choices:

• Increase the size of the photomask that contains the pattern to be printed on the wafer

• Reduce the size of the imaging field of view

The first option is not only a huge technical challenge, but also has many knock-on effects because the current mask infrastructure is designed around standard 6-inch square reticle infrastructure. Even at current sizes, producing defect-free mask blanks is an obstacle to low numerical aperture development, and area scaling to 2x or 4x is not easy.

Actinic mask inspection tools, which use low-power EUV light sources to inspect EUV masks, have only recently become available and are designed around the 6-inch standard. EUV masks and infrastructure are already many times more expensive than their DUV counterparts, and costs are also many times higher as area scales rapidly expand.

Option 2 seems to be the lesser of two evils. While it also poses serious technical challenges, it does not require significant changes to the lithography ecosystem beyond the scanner. The chip manufacturer fully supported the second option, and ASML began development work that will soon culminate in shipments of the first High NA machine, the EXE:5000.

These architectural decisions have some key implications: technical challenges with half-field stitching, depth of focus, and photoresists, as well as cost challenges compared to existing low numerical aperture tools. We'll explore each of these in turn.

A lithography scanner exposes the wafer through an exposure slit. The wafer is moved or scanned under the slit to expose the pattern on the photomask onto the wafer. Once the entire mask pattern is exposed, the scanner walks to a new area of ​​the wafer and repeats the scan. The exposure field is the area covered by a complete exposure of the mask.

You can see this step-and-sweep motion in the ASML gif below. Keep in mind that the movement is fast enough to cover hundreds of wafers per hour, and the pattern placement accuracy is down to the nanometer, near atomic level - it's incredible how it works.

The exposure field size of high numerical aperture scanners is only half that of low numerical aperture EUV and traditional DUV tools. This is a "lesser of two evils" trade-off, allowing increased lens size while maintaining industry standard photomask sizes.

One of the "downsides" in this trade-off is having to mix half-field and full-field exposures on the same wafer. High numerical aperture will be used only for the few most critical layers, i.e. the layers with the smallest features to be printed. Others will use cheaper tools with loose imaging capabilities. This means that mask layout and die size must be planned with half-field and full-field imaging in mind. This will certainly be an issue for future chip designs, given that a poorly optimized mask layout can result in high cost despite a smaller chip size even without adding half-field complexity.

There are a lot of issues here that chip designers should be acutely aware of. Back to the main topic, cost and functional fidelity.

In order to understand the cost impact of high numerical aperture architectures, we need to understand the concept of scanner exposure dose and its impact on throughput. The cost of lithography is mainly determined by the cost of lithography tools (scanners). The latest low numerical aperture NXE:3800E tools now cost over $200 million each, so the scanner cost per wafer produced depends primarily on the scanner throughput.

Dose is a measure of the energy reaching the wafer. This energy creates a chemical reaction in the photoresist, changing it from insoluble to soluble and vice versa. Patterning smaller features usually requires higher doses to avoid various errors. Crucially, to reduce CD, dosage requirements increase exponentially.

Why is this important? Because dosage affects throughput and therefore cost. Higher doses require more powerful light sources and slower scanner speeds.

ASML has been reliably increasing source power with each new EUV model, but not enough to keep up with exponentially increasing dose requirements. This means that the scanner must slow down so that each exposure field receives at least the minimum dose.

In short: Lithography costs increase dramatically as critical dimensions decrease because dose requirements increase dramatically. Higher dosage means you need to buy more tools to produce the same number of wafers.

It turns out there is a readily available high numerical aperture alternative: low numerical aperture dual patterning. Already used by some leading node chipmakers, it requires 2 exposures using low numerical aperture EUV tools to print a single layer. The CD requirement for each exposure is approximately twice the final feature size. This has the highly desirable effect of requiring much lower doses because you are operating further down the exponential dose versus CD curve.

At these lower doses, the scanner can reach its full potential; throughput will be limited by wafer and mask stage speed, not dose.

The throughput advantage of low numerical aperture dual patterning is so strong that despite requiring twice as many wafers to pass through the scanner, the lithography cost is lower than that of a high numerical aperture single exposure. Our models suggest this is true from the current leading 3nm process node to the 1nm equivalent process node that may be launched in 2030.

Cost normalized to low numerical aperture 3nm, utilizing ASML's best available low numerical aperture and high numerical aperture lithography tools during the year, and providing a roadmap for source and stage improvements.

For all these nodes, even if ASML achieves the stated goal of 1 kW source power for 1nm nodes in time, High NA throughput will be limited. The simple reason behind this is the rapid increase in dosage requirements that we detailed in the previous section. The impact of running further along the exponential dose versus CD curve hurts throughput so much that the cost advantage of low-NA dual patterning increases between the 2nm and 1.4nm nodes despite shrinking CD.

And, ironically, the faster stages developed for High NA will be back-ported to future Low NA models, thereby increasing their throughput and further increasing their cost advantage over High NA because of the low dose of Low NA Tools are subject to more stages.

It is also worth considering the impact if the source power cannot be increased to 1kW. Higher light source power accelerates wear on projection optics and photomasks because reflective coatings are subject to deleterious effects such as increased thermal loading. The current higher power of 600W may increase optics wear to unacceptable levels - these are the most expensive components in a scanner and will incur high costs if replaced after a short service life.

If we assume that source power cannot be increased in the future, this does not change the inflection point at which high numerical apertures become more cost-effective, but it does mean that lithography costs overall will increase significantly at future nodes compared to existing nodes. Engraving costs will increase by up to 20%. Current 3nm baseline.

This is just an assumption at the moment, as the light source power has been increasing with every new EUV scanner model so far, although not as fast as the major fabs would like.

As it turns out, ASML's public materials support our cost conclusions. Traditionally, new generation scanners have been sold at a higher price but lower cost per wafer compared to existing tools. This makes sense for chipmakers because they are primarily optimizing for cost per wafer if the scanner meets imaging performance requirements. ASML is also happy because they are selling more expensive scanners.

As recently as 2020, this was a high numerical aperture assumption; it was said to have cost advantages compared to lower numerical aperture dual patterns.

But starting in 2021, the metric of choice will change from cost per wafer to process complexity. While reducing complexity is great, it is not the primary driver of fab equipment decisions. Chipmakers who run wafer fabrication processes with more than 1,000 steps are accustomed to complexity. They plan their fabs and purchase equipment based on cost and projected throughput, where lower numerical apertures seem to perform better.

At 1nm and 7A nodes, now in the 2030+ time frame, the cost gap is finally closing. Driving this trend is a paradigm change from geometric scaling to stacking—not horizontal shrinking of capabilities, but vertical stacking of capabilities to achieve chip performance power and area improvements. This means that CD requirements remain the same, so continued advances in photoresists and source power bring high numerical apertures closer to parity.

We see the change from 2d scaling to 3d scaling and the resulting slowing down of CD shrinkage, which is the natural location for High NA insertion. This dramatically changes the intensity of lithography for advanced logic manufacturing.

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