Advanced packaging, in one fell swoop

When we stand at the node of 2023 and talk about chip performance, everyone seems to have reached a consensus that advanced processes are no longer the key to improving performance. It has become extremely difficult to double the chip transistor density every two years, whether it is TSMC, Either Samsung or Intel will consume several times or even more than ten times the investment to advance the process by 1nm. In short, advanced processes are becoming increasingly uneconomical.

At this time, advanced packaging began to emerge, represented by Apple and TSMC, starting a new revolution. It is mainly divided into two categories. One is advanced packaging technology based on XY plane extension, which mainly uses RDL for signal extension and Interconnection; the second is advanced packaging technology based on Z-axis extension, which mainly uses TSV for signal extension and interconnection.

The former is 2D advanced packaging, represented by FOWLP and FOPLP, etc., while the latter is 3D packaging, represented by SoIC and Foveros, etc. There are currently 2.5D packages that combine the characteristics of both packages, represented by CoWoS and EMIB.

Currently, 3D packaging is mostly used to improve the performance of HPC chips, and is commonly seen in chip integration between HBM and processors such as CPU, GPU, FPGA, or NPU.

For example, the SoIC integrated packaging architecture proposed by TSMC mainly uses W2W and C2W hybrid bonding technology to achieve I/O node interconnection below 10um, reduce parasitic effects, and make the chip thinner.

Samsung launched a 3D packaging technology called X-Cube in 2020, which stacks four SRAMs on a logic core computing chip and connects them through a TSV structure.

Intel launched a 3D logic chip packaging technology called Foveros at the end of 2018, which uses TSV and Micro Bumps to stack and connect different chips in a Face-to-Face manner. Currently, Foveros technology can enable the bump pitch to reach 50um, and it is expected to be reduced to 10um in the future. Let the number of bumps reach 10,000 per square millimeter.

Among these packaging methods, the main purpose is to integrate different types of chips through 3D stacking to achieve the target advantages of high performance, small size, and low power consumption, that is, heterogeneous integration.

Wire Bonding, the earliest method used in packaging, has a limited number of I/O contacts because its contacts can only be arranged in a row around the chip. Flip Chip Bonding, proposed by IBM, uses solder Micro-bumps (Solder Bump) are used as contacts to bond chips together. The contacts are arranged in an array and can be distributed on the entire chip, which can increase the number of contact I/Os. However, this technology is limited when the pitch is 50μm or 40μm. While the performance was acceptable, it was quickly discovered that this approach would cause warping and chip shifting due to thermal expansion mismatch.

In fact, once the micro-bumps reach a pitch of less than 10 microns, the exposure problems become more and more serious. When the bump structure is larger, there is minimal unevenness in the height of the electroplated micro-bumps or changes during the reflow soldering process. It may be negligible, but with fine-pitch microbumps, these small variations can lead to poor joint formation and impact electrical yield, ultimately leading to defects in the die and package.

Cu-Cu Hybrid Bonding technology emerged as the times require, embedding metal contacts between dielectric materials, and simultaneously using heat treatment to join the two materials, using the atoms of copper metal in the solid state Diffusion to achieve bonding, so there will be no Bridging problem. The copper process is a very mature technology in the semiconductor industry. The pitch of copper-copper contacts can be reduced to less than 10 μm. Therefore, more than one million contacts can be produced in a 1×1cm² wafer. Therefore, direct bonding of metals has become very important. .

Hybrid bonding, previously commonly known as DBI (Direct Bond Interconnect) in the industry, was first proposed in the mid-1980s by Paul Enquist, QY Tong and Gill Fountain in the laboratory of Research Triangle Institute (RTI). Technology, the trio founded Ziptronix in 2000 and in 2005 introduced a technology called low-temperature direct bonded interconnect (DBI), the first version of hybrid bonding.

It verified the feasibility of low-temperature direct bonding (Direct Bond Interconnection, DBI). First, prepare the wafer with SiO 2 (dielectric material) and copper (contact metal). At this time, the copper part will be slightly lower than the dielectric material. Thickness, use plasma (Plasma) for surface activation treatment, and align the wafers face to face at room temperature. Due to the van der Waals force, it already has a certain bonding strength. Then, maintain the temperature at 100°C to let SiO 2 and SiO 2 A condensation reaction occurs between them to form a strong covalent bond to increase the bonding strength. Then increase the temperature to 300°C to 400°C and maintain the temperature. At this time, because the thermal expansion coefficient of copper metal is larger than that of SiO 2, the copper surfaces will touch together and naturally receive a compressive stress, prompting the copper contacts to diffuse. Engagement.

Some researchers pointed out that in order to achieve low-temperature bonding, the height difference between the dielectric material layer and the metal layer after chemical polishing and grinding will be the key. The choice of grinding fluid and grinding parameters is the main reason for the different thicknesses. The thickness difference The smaller it is, the lower temperature can be used to bring the copper surfaces into contact and initiate bonding.

The hybrid bonding and flip-chip bonding ratio brings three new advantages. The first is that it can achieve ultra-fine pitch and ultra-small contact size to achieve a higher number of I/Os; the second is that the bottom is replaced by dielectric material bonding filler to further save filling costs; thirdly, flip-chip technology will allow a thickness of about 10 to 30 μm between the chip and the substrate or between the chips, while hybrid bonding has almost no thickness, which can be significantly reduced in the case of multi-layer stacking Overall thickness.

At present, copper-copper hybrid bonding is mainly divided into three methods, namely the most common wafer-to-wafer (W2W) process, chip-to-wafer (D2W) and chip-to-wafer (C2W) processes. The latter two processes It is still under development.

Among them, although W2W has achieved mass production, its size limit for the upper and lower chips must be the same size, otherwise there will be a waste of area; D2W is to stick the cut Die to the wafer by temporary bonding, and then the whole chip The die is bonded to another product wafer in its entirety and then debonded. This technology is prone to accumulating errors and has high costs. It also has high requirements on the thickness variation range of the die. C2W will place the cut die at the corresponding positions of the wafer. Although the position accuracy has improved and the thickness change requirements are no longer stringent, particle control is also an issue that affects its continued popularity.

In 2015, Ziptronix, which invented hybrid bonding technology, was acquired by Xperi. In 2019, Xperi completed the final patent layout of hybrid bonding technology. Before that, this technology had been licensed to many manufacturers, including Sony.

From its conception in the 1980s, to preliminary verification in 2005, and then to technology authorization after 2015, hybrid bonding has finally paved the way for advanced packaging and solved chip manufacturers' concerns about the future of packaging. The biggest doubt is that since then, the field of hybrid bonding has shown a scene of thousands of sails competing.

In 2016, Sony first applied hybrid bonding technology to the backside-illuminated CMOS Image Sensor (BI-CIS) of the Samsung Galaxy S7, significantly improving the lens resolution. Sony currently ships millions of CMOS image sensors every year using 6.3 micron pitch hybrid bonding technology and stacking 3 chips, while other companies use much lower pitch density and ship much smaller volumes.

As a pioneer in this technology, Sony will demonstrate 1 micron pitch face-to-face hybrid bonding and 1.4 micron back-to-back hybrid bonding in 2022. The reason why it is so radical is that it hopes to continue to decompose and stack image sensors through this technology pixels to capture more light and data, turning it into actual photos and videos.

SK Hynix will mass-produce hybrid bonding as early as 2025 and prepares to use it for HBM4 products. Compared with existing processes, hybrid bonding improves heat dissipation efficiency and reduces wiring length, allowing for higher input /Output density, capable of increasing the current maximum stack of 12 layers to 16 layers. Ki-il Moon, head of technology development at SK Hynix PKG, said: “We are focusing on the development of this technology (related to hybrid bonding) and have actually achieved meaningful production. The technology will be available in 2025~2026. years of commercialization.”

In August 2020, Samsung demonstrated its own 3D packaging technology - X-Cube, full name "eXtended-Cube", which stacks the SRAM layer on top of the logic layer, allowing multi-layer ultra-thin stacking, it said Samsung foundry is developing ultra-fine pitch copper-copper hybrid bonding, which has achieved pitches of less than 4 microns.

Intel announced a new hybrid bonding technology at the IEEE International Electronic Devices Conference in December 2022. Gaijishu will continue to shrink the interconnect pitch to 3 microns. Intel has achieved the same goal as the monolithic system-on-chip (system-on-chip). ) connects similar interconnect densities and bandwidths. Compared with the results announced at IEDM 2021, Intel's latest hybrid bonding technology demonstrated at IEDM 2022 has improved power density and performance by another 10 times.

In addition, in June 2002, CEA-Leti and Intel announced a new hybrid bonding self-alignment process that uses the capillary forces of water droplets to align the die on the target wafer. This process has the potential to increase calibration accuracy. As well as manufacturing throughput of thousands of chips per hour, the state-of-the-art alignment for post-bonding with pick-and-place tools is 1µm, best case 700nm, while new processes offer sub-500nm and even sub-200nm post-bond pairs allow.

Eric Beyne, imec senior researcher, vice president of R&D and director of the 3D system integration project, said in a paper at IEDM that imec's current research has proven the feasibility of hybrid bonding at a 7-micron pitch. imec officials stated that using this technology, the 3D interconnection density between chips or between chips and silicon interposers is more than sixteen times higher than existing technology. It has developed inter-chip pitches as small as 3μm and high tolerance pick and place accuracy. Hybrid bonding.

TSMC is undoubtedly the master of hybrid bonding. Its SoIC packaging technology relies on hybrid bonding to achieve strong bonding pitch scalability on chip I/O and achieve high-density chip-to-chip interconnection. Its bonding pitch Starting below 10 microns, TSMC says short chip-to-chip connections offer smaller form factors, higher bandwidth, better power and signal integrity, and lower power consumption than the industry’s most advanced packaging solutions today. advantage. Previously, TSMC has demonstrated the research results of its fourth-generation hybrid bonding technology, which can achieve 100,000 contacts per square millimeter.

At the end of 2021, AMD introduced the TSMC hybrid bonding technology they had adopted on server processors. At the beginning of 2022, AMD announced that Ryzen 7 5800X3D also used Hybrid Bonding technology to superimpose 7nm SRAM on the 7nm processor. Copper─ Copper hybrid bonding can increase contact density by 200 times and reduce the energy required for each signal transmission to less than one-third.

It is worth mentioning that the Xtacking architecture launched by Yangtze Memory in China uses W2W hybrid bonding technology, using different processes to produce Memory wafers and CMOS wafers successively, and build the two in the back-end process. Contacts. Through hybrid bonding, these contacts are connected by links, and Memory and CMOS are interconnected in the vertical direction.

Yangtze Memory officially stated that hybrid bonding enables billions of metal channels to be connected on 3D NAND flash memory. As the number of layers continues to increase, 3D NAND flash memory developed and manufactured based on crystal stack Xtacking will have more cost and innovation advantages.

For this emerging technology, equipment manufacturers have not stayed away. Hybrid bonding is a back-end process. Its equipment is mainly provided by Germany's Karl Suss (Karl Suss) and Austria's EVG (EV Group). Japan's Canon and Mitsubishi are also currently interested in developing this bonding equipment, but their current market share and technical level are still far behind those of European manufacturers.

For hybrid bonding technology, the current largest application method is still stacked CIS represented by Sony. After several years of optimization, the current CIS field is very comfortable in using this process, and it is expected to achieve greater success in the future. large-scale mass production.

The second largest application field is undoubtedly DRAM and NAND. We can see the active layout of Samsung, Hynix and Yangtze Memory in this area. Some manufacturers have already produced certain results. We may see it in 2025. Hybrid bonding technology has been put into mass production in this field.

The final application scenario is 3D advanced packaging represented by TSMC's SoIC technology, which has been mass-produced on AMD processors. In the future, Apple is also expected to adopt this technology on the M-series processors installed in MacBooks. Large-scale production may also be around 2025.

Improving chip performance used to look at the manufacturing process, but now we look at packaging, which looks towards heterogeneous integration. The past difficulty in heterogeneous integration was bonding. Nowadays, copper-copper hybrid bonding is becoming increasingly mature, and the interlocking processes behind it are expected to realize chip implementation. The next leap in performance, we firmly believe that this day is no longer far away.

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