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The first chapter of Romance of the Three Kingdoms states it clearly: "As the general trend of the world goes, things that have been divided for a long time will eventually unite, and things that have been united for a long time will eventually divide." This sentence is also very appropriate to describe chips.
Chips were single-function chips in the early days, and evolved to multi-function multi-chip modules (MCMs), to systems on a chip (SoCs), to systems in a package (SiPs), and finally to the so-called chiplets. These separations and integrations are closely related to semiconductor manufacturing processes, packaging and testing technologies, and even system-side applications.
In the earliest system applications, various ICs with different functions were integrated together in the form of printed circuit boards. However, as the operating frequency required by the system becomes higher and higher, and the size is reduced, it has become a trend to integrate several core ICs in the same package to shorten the transmission distance between them, and multi-chip packaging technology (MCM) has emerged. In addition, SiP, heterogeneous integration, and even 3DIC are more advanced packaging methods, which technically include chip stacking. In short, if the chip design or wafer process cannot meet the needs of the system, a solution will be sought in the packaging. Therefore, chip design, wafer production, and packaging and testing are three pillars, and they have their own gains and losses with time and technological evolution.
Known good die (KGD) is a big challenge in multi-chip packaging. Usually, a chip must be packaged before it can be fully tested and shipped. However, if multiple bare chips are packaged together in a module, if it is not possible to ensure that each bare chip is a good product, it will inevitably cause a significant loss in yield. In order to ensure that each bare chip is a good product, the industry has vigorously developed on-wafer testing technology (chip probe), which includes complex probe cards and testing equipment, and these products have also formed an important link in the overall industry chain.
As wafer manufacturing technology becomes more mature and advanced, wafer fabs can provide transistors with different operating voltages or breakdown voltages in the same process. At the same time, embedded memory, such as flash memory, EEPROM, and OTM (one time memory), which play an important role, can also be implemented one by one in the same wafer. Thus, the architecture of the system-on-chip is finally integrated and can be implemented by combining logic operations, analog circuits, memory, and even high-voltage power management.
Apple's M1 chip can be said to be the pinnacle of the current system-on-chip, integrating the Arm architecture CPU, GPU, AI neural network acceleration engine, and the fabric bus interface that connects these units. Compared with the x86 architecture, the M1 chip has the advantages of high performance, low power consumption, and high integration. The M1 Max chip contains 57 billion transistors, making it the leader in current personal computer chips.
Another extreme of the system-on-chip is NVIDIA's GPU. NVIDIA's latest generation of Hopper GPU contains 80 billion transistors, 15,000 cores, and uses TSMC's 4-nanometer process. The length and width of each chip are nearly 3 centimeters. This giant chip directly challenges the yield of the wafer fab and the subsequent packaging test, and the effective area of each 12-inch wafer will also be affected. Assuming that the demand for high-performance computing (HPC) chips in the system continues to increase, when the area of a single chip can no longer be increased, it is necessary to start making appropriate cuts, which is why small chips are proposed.
It is worth mentioning that NVIDIA GPUs have always been named after famous scientists, such as Ampere, Volta, Pascal, etc. Hopper is a famous American female computer expert, a rear admiral, and her name Grace is also named after NVIDIA's first CPU to be commercialized.
The introduction of chiplets not only alleviates the challenge of the continuous increase in chip area, but also allows the blocks with different functions within a single chip to be divided and implemented under different process conditions. For example, the core of the chip is implemented with 5 nanometers, and its I/O or main control bus part can be implemented with a more mature process to further optimize costs. Therefore, the transmission communication protocol between multiple chiplets is very important, which is also the interface standard UCIe (Universal chiplet interconnect express) proposed by the Chiplet Alliance. In fact, this is the specific implementation of heterogeneous integration, in other words, it is an advanced version of SoC, system on integrated chips (SoIC).
In this trend of chip integration, a newly established chip design company went against the trend and made the entire 12-inch wafer into a single high-speed computing chip. The side length of the chip is more than 20 cm and contains 1.2 trillion transistors. The reason is that in the future, the energy lost by the chip in transmitting one bit will be greater than the energy required to calculate one bit, and this design can increase the frequency of operation. Whether this approach will lead the trend, we will have to wait and see.
The 18-inch wafer project, which was a hot topic more than a decade ago but was aborted, has recently been proposed by interested parties to cope with the increasingly large single chips. It seems that semiconductor R&D personnel have been challenging problems and proposing solutions to them, and have been moving forward on the road of separation and integration.
*Disclaimer: This article is originally written by the author. The content of the article is the author's personal opinion. Semiconductor Industry Observer reprints it only to convey a different point of view. It does not mean that Semiconductor Industry Observer agrees or supports this point of view. If you have any objections, please contact Semiconductor Industry Observer.
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