ADI Small Classroom丨Today we will analyze a precision Σ-Δ ADC with examples

Figure 1. AD7175x Σ-Δ ADC family; AD7175-2 block diagram and noise performance

The AD7175-2 has a very useful software tool to aid in evaluation. Eval+ is a single software download from the ADI website that is used to configure, analyze, and select the ADC with or without hardware. When the software is run with the hardware, it behaves like a standard evaluation board. Without the hardware, a functional model of the ADC runs in the background, allowing the user to establish the best operating configuration for their end application.

Figure 2. Configuration tab of the AD7175-2 Eval+ software in functional model evaluation mode.

Table 1. AD717x Family Overview, Showing Available Channel Count Options and Pinout Correspondence of Family Members

The AD7175 ADC is used to illustrate how digital filtering can be used to eliminate the quantization noise of a Σ-Δ ADC. The key is the trade-off analysis of noise/input bandwidth and settling time.

Figure 4 shows the raw modulator noise sources versus the logarithm of the frequency from DC to FMOD/2 (or 4 MHz) for the AD7175 device. The AD7175 modulator samples at an effective rate of 8 MHz (FMOD). The modulator is a MASH type that provides an 80 dB/decade attenuation rate for the modulator noise. The thermal noise of the circuit determines the noise floor in the band before the modulator noise begins to ramp. The high dynamic range capability of this ADC for low bandwidth signals can be seen in the curve showing the low noise floor. This dynamic range, along with the AD7175’s ability to reduce the noise floor, can be used to improve the sensitivity of the application, which is especially useful when acquiring low amplitude signals.

The minimum oversampling ratio of the ADC, the digital filter order, and the corner frequency all help ensure that the quantization noise is not the limiting factor of the ADC noise. To filter out the noise, the envelope of the filter 0ca7d2 must be able to attenuate at a large enough roll-off rate to cope with the increasing rate of amplitude quantization noise.

The minimum oversampling ratio of the AD7175 is ×32, which gives a maximum output data rate of 250 kHz at 8 MHz FMOD.

The AD7175 offers several different types of filters that the user can choose from. The operation of the digital filter is illustrated by comparing the sinc5 + sinc1 and sinc3 filters in different situations.

At 250 kHz ODR, the AD7175 sinc5 + sinc1 can be directly configured as a sinc5 with a −3 dB frequency of ~0.2 × ODR (50 kHz). The attenuation envelope of the sinc5 filter is −100 dB/decade. This means that the attenuation and roll-off rate of the sinc5 filter is sufficient to remove the modulator noise, as shown in Figure 3.

Figure 3. AD7175 modulator output spectrum DC to FMOD/2 using sinc5 + sinc1 and decimation by 32 (yielding sinc5 DC response).

Figure 4. AD7175-2 sinc5 + sinc1 filter: Adjusting input bandwidth by changing the ADC decimation rate.

In contrast, if we change to a sinc3 at 250 kHz ODR, the attenuation and roll-off rate will not be sufficient to remove the modulator noise. The noise numbers at 250 kHz and 125 kHz ODR in the data sheet illustrate this. Only by setting the data rate to 62.5 kHz or lower will the sinc3 response completely filter out the quantization noise from the ADC result.

In addition to filtering out quantization noise, digital filters can also reduce noise by adjusting the input bandwidth. This is accomplished by increasing the decimation rate. For the sinc5 + sinc1 filter, increasing the oversampling ratio means that the initial fifth-order sinc filter is averaged. Using the average of the initial results, the user can select different output data rates, speeds, and bandwidths to improve noise performance (as shown in Figure 5), which is improved by averaging sinc5 and then sinc5 + sinc1. Averaging the sinc5 results will introduce first-order notches at the output data rate and multiples of the frequency, which will be compounded with the sinc5 overall envelope. The notch frequencies in sinc-type filters are traditionally used to reject interfering signals of known frequencies, that is, by strategically setting the data rate to coincide with the interfering frequency. A classic example is 50 Hz and 60 Hz power frequency rejection.

Figure 5. AD7175-2 sinc5 + sinc1 filter – noise vs. ODR

The sinc filter is a moving average filter with a sin(x)/x profile, so it is generally called a sinc filter. The filter consists of a series of integrators, a switch used as the decimation rate, and a series of differentiators. It is a finite impulse response (FIR) type filter. For a step change in the input, it exhibits a known and finite linear phase response. Deep notches occur at the output data rate and its integer multiples, and the signal within the notch is attenuated.

Figure 6 compares the third-order and fifth-order sinc filters of the AD7175, both running at a decimation rate of 32. In this case, both filters provide conversion data at an output rate of 250 kHz. The order of the filter determines the roll-off rate and the −3 dB frequency. The sincP filter sits below the frequency response envelope of –P × 20 dB/decade. The steeper the roll-off, the lower the −3 dB frequency. The main difference between filters of different order is the filter settling time, which can have different impacts on the end measurement application depending on the situation.

Figure 6. Frequency domain comparison of different order sinc filters: sinc5 and sinc3

When the digital filter processes the moving average of the data stream from the sigma-delta modulator, there is an associated settling time. This delay is fixed for all FIR filters, but it is different for different order sinc filters. This delay is usually described by two terms: group delay and settling time. Group delay describes the delay from the presence of an analog signal at the input to the time it is seen at the digital output. For example, for a single-tone sine wave, the group delay is the time difference from the presence of the sine wave voltage peak at the analog input to the time that peak appears at the digital output.

Settling time refers to the total averaging time of the digital filter. If there is a step at the analog input, it will take the full settling time of the filter before the data output of the ADC is independent of the input before the step. There may be other delays, such as calculation time of the filter. For the AD7175 series, the first conversion will have a longer settling time; settling after leaving the standby state may also cause delays due to the initial calculation cycle of 1/ODR. Delays other than the filter settling time may vary depending on the converter selected, so be careful when reading the ADC data sheet.

The effects of filter settling time can be better illustrated by comparing a single Σ-Δ ADC to a multiplexed Σ-Δ ADC. The settling time of the digital filter has a significant impact on the rate at which multiple input channels can be converted in a loop, keeping the results from each channel independent.

Why wait for the full settling time to give an independent result? Let's look at digital filtering of a single-channel ADC with a single input source. Data from the Σ-Δ ADC modulator is sent to the digital filter at a rate of FMOD (as shown in Figure 5), and each sample passes through a moving average filter. Depending on the order and type, the filter weighs each sample differently during the conversion period (set by the filter decimation rate), as shown in Figure 7.

Input sample 0 and subsequent samples are the discrete output results of the modulator at each of its clock cycles. The y-axis represents the proportion of weight given by the digital filter to each sample. The shape of this weight is the time domain representation of the low-pass digital filter. The output data rate in this case is 250 kHz (8 MHz/32 = F _MOD / decimation rate). The time between data ready signals (vertical dashed lines of various colors) is 4 μs. The ADC is running with a sinc5 + sinc1 filter and a decimation rate of 32. When defining the filter output as the analog input of the modulator, all five conversion outputs have some overlap, so no output is independent. For a single ADC input, each conversion result shares the modulator analog input, but the filter weighs each modulator output with different weights.

Figure 7. Single ADC input, sinc5, and five conversion output cycles.

For multiplexed inputs, each conversion data generated by the modulator must be independent for each channel. The filter’s full settling time must pass before the multiplexer can switch from one analog input channel to another. For a sinc3 filter, for example, using a 32x decimation rate, the filter settling time for one conversion is shown in Figure 8(a). Once the filter is fully settled, the data output is a weighted average of the previous 96 modulator outputs. This is equivalent to an ADC output data rate of 12 μs or three cycles.

Figure 8(b) shows the first three samples of the multiplexed case, with each sample at the ADC output fully settled. There is no overlap of the modulator output between any of the samples. The multiplexing rate, indicated by the time between the DRDY (vertical lines), is determined by the settling time of the filter. This rate is often described in data sheets and performance plots as the fully settled data rate.

Figure 8. Multiplexed ADC, sinc3 filter, and three conversion cycles—fully settled data.

For a sincP filter, the settling time of the filter is the filter order P multiplied by 1/ODR. For a sinc3 filter running at an ODR of 250 kHz, the settling time is 3 × 1/250 kHz = 12 μs. In comparison, if a sinc5 filter is used with the same ODR of 250 kHz, the settling time is 5 × (1/2 50 kHz) = 20 μs.

The approximate channel switching rate is the ODR divided by the filter order, which is ODR/3 (for a sinc3 filter) or ODR/5 (for a sinc5 filter). For a straight sinc filter, this is obvious. For a sinc5 + sinc1 type filter, an additional step is required. The AD7175 family of ADCs allows for the selection of different types of filters. The next section will explain the differences between the different types of filters and provide an example of how to calculate the settling time for each case.

Now let's look at the settling time in a multiplexed case. In process control and factory automation, a typical analog input module will have a front-end conditioning to scale the ±10 V inputs to the input range of the AD7175-8. The AD7175-8 will then multiplex each channel and convert each input or pair of inputs sequentially. The time to complete the conversion of all channels depends on the filters used and the number of channels.

In the following example, we will see a comparison and method for calculating the settling time by comparing the use of a sinc3 filter and a sinc5 + sinc1 filter, both configured for the same output data rate. The user can select these two filter options for the AD7175-8.

Notice there are two parts. The sinc5 filter averages over a 4 μs window (FMOD = 8 MHz), so it passes data to the averaging block at a rate of 250 kHz.

Note: For the sinc5 + sinc1 filter, the ADC has a single-cycle settling characteristic at data rates of 10 kSPS and below. This means that the ADC settles in 1/ODR.

Table 2 shows a comparison of a 4-channel multiplexed measurement using setups (a) and (b). Using sinc5 + sinc1 filters increases the sample rate per channel, showing the advantage of faster settling time. Note: This rule of thumb applies only to the converter, if there is an analog preconditioning circuit before each input and its time constant is longer than the ADC, then the worst-case settling time will dominate.

Table 2 shows the comparison results:

Table 2. Comparison of per-channel data rates for Sinc5 + Sinc1 and Sinc3 filters for a 4-channel multiplexed system (for example, using the AD7175-8).

That was a brief introduction to Σ-Δ ADCs—the principles surrounding the modulator, the concept and examples of digital filtering, and its impact on noise, settling time, and some of the knock-on effects within a measurement system.