How to deal with supply chain problems? Chip testing solutions are here!

According to Counterpoint data, as of the beginning of 2021, the top three mature process (>40nm) production capacity are TSMC (28%), UMC (13%), and SMIC (11%). From the perspective of mainland China, SMIC provides 1/3 of the wafer production capacity. There are many different reasons for the tight production capacity, which can be summarized as follows:

(1) COVID-19 outbreak

On the one hand, the epidemic has changed our traditional work and lifestyle, and the demand for electronic products for remote work and indoor entertainment has increased sharply. On the other hand, the epidemic has caused some foreign factories to shut down, further exacerbating production capacity constraints.

(2) Explosive growth of start-up chip design companies

In recent years, with the strong support of national policies, domestic newly established chip design companies have sprung up like mushrooms after rain. The number of chip design companies has increased from 1,380 in 2017 to 2,218 in 2020, and it is very likely to exceed 3,000 in the next two years. The semiconductor industry is in short supply of talent, salaries are rising, and production capacity has become tight and prices are soaring.

(3) Production increase and expansion in the mainland is hindered

Affected by geopolitical factors, the expansion of wafer production capacity in mainland China has been curbed to a certain extent in terms of both equipment and talent.

(4) Wait-and-see attitude towards the expansion of mature processes

Some international giants have reservations about expanding mature production capacity. Since wafer fabs have a long construction cycle and require large investments, if the production capacity of mature processes is expanded blindly on a large scale, once there is "oversupply", it may not even be possible to recover the investment, let alone make a profit.

(5) Supply chain security considerations

When chips are in short supply, operations managers will use over-booking, stockpiling, etc. to ensure the delivery security of the supply chain. The "bullwhip effect" causes the demand for production capacity to be abnormally amplified.

The situation of my country's chip companies is like looking for water in the desert. Before we find a new water source, we must cherish every drop of water in the bottle. In the case that the problem of "capacity shortage" cannot be solved in a short period of time, cherishing every wafer and every chip in our hands has become our inevitable choice.

With limited production capacity, the yield rate determines the number of chips we can ultimately deliver. Based on a shipment volume of 100kk/year, a 1% yield rate increase will result in an additional 1kk/year of chips. Since the chip design NRE and manufacturing costs have already been paid, the vast majority of the revenue generated by this 1kk chip is net profit!

During the entire chip manufacturing process, the yield is affected by different factors at each stage, including design, manufacturing process, materials, packaging, testing and many other factors. Among them, since testing accounts for a small proportion of the chip manufacturing cost, the yield loss it brings is usually the most easily overlooked. So how to improve the yield through "chip testing"? There are two paths for everyone to think about:

• Path 1: Carefully design test plans, take test mass production seriously, and use excellent test engineering capabilities to directly improve test yield by reducing overkill without sacrificing product quality.

• Path 2: Make full use of chip characteristic test results, explore and analyze mass production test big data, and provide feedback to key links such as chip design front-end and back-end, wafer process, and chip packaging, indirectly promoting the improvement of product yield.

In path 1, optimization can be performed in many aspects, including the performance and stability of the ATE test machine, the setup of ATE/prober/handler, the design/reliability of the test fixture, the test limit, test coverage, and test program optimization, so as to improve the yield without sacrificing product quality.

In Path 2, data from engineering verification, mass production, system-level testing, reliability testing, and other aspects at the wafer and finished product ends are all powerful tools for improving chip design, wafer manufacturing, and chip packaging.

There is also a kind of feedback from end customers, "RMA", which is very expensive data! Take the mobile phone market as an example. In the past 15 years or so, the domestic mobile phone manufacturers that finally won the competition have been raising their requirements for chip quality. "Copycat mobile phones" are a thing of the past. The quality requirements for single products have increased from 1000DPPM a few years ago to 500DPPM, and then further to 200DPPM. In contrast, a certain international manufacturer has always required 50DPPM for the quality of single consumer chips, empowering product value with excellent quality, far ahead of its peers. From the three dimensions of product level, company level, and international perspective, the pursuit of excellent quality is the core competitiveness of the company's long-term development and victory in the journey to the "stars and the sea".

With the help of "chip testing", we can get more chips by improving product yield, and get better chips by improving quality. To achieve these two goals, we need excellent "testing capabilities".

Specifically speaking, excellent "testing capabilities" should have the following four characteristics:

• Excellent test solution development capabilities , including an engineering team with extensive experience in test software and hardware development, project management and delivery, test engineering and product engineering.

• ATE test equipment with up-to-standard performance, strong stability and high cost performance . Does the best test solution necessarily require the best-performing and most expensive ATE test equipment? This is not the case. Practical experience tells us that the most suitable one is the best.

• Complete hardware and software facilities, standard factory buildings, excellent factory management team and deeply rooted quality concept . How should traditional testing factories be upgraded to meet customers' needs for delivery cycle and delivery quality? How can we provide customers with more timely, reliable and engineering-capable support and services?

• Do a good job of DFT/DFM (reliability/manufacturability) . An African proverb goes, “The best time to plant a tree is 20 years ago. The second-best time is now.” Similarly, “The best test is DFT testability design.” Avoid the “filling holes” problem in the test development phase, thereby saving engineering resources, reducing test costs, and improving product quality.

  
  

As a domestic one-stop supply chain platform service company, Moore Elite serves many chip design companies in the testing field through a strong engineering team, self-operated + third-party testing plants with rich production capacity, and independently controllable ATE equipment.

• Strong engineering team: We have a professional AE engineering team of more than 50 people at home and abroad, many of whom have been working in the chip testing industry for more than 30 years to better serve our customers;

• High-quality self-operated factories + third-party testing capacity: over 100 units of capacity solve the shortage problem, and high-quality management improves the quality of the supply chain;

• Cost-effective, self-controllable ATE equipment: high-quality performance, stable quality, Moore Elite self-controllable to ensure supply chain security;

• The Chinese localization team leads the research and development of the next generation of ATE, and the international technical team collaborates and supports to break through the technological blockade.

• Positioning : Cost-effective general-purpose chip automatic test mass production equipment

• Advantage :

(1) Mature technology: the result of 20 years of R&D and iteration by a leading American international semiconductor company;

(2) Reliable performance: verified by large-scale mass production of tens of billions of chips;

(3) Strong versatility: Digital + analog + mixed signal + RF test resources can meet the mass production test needs of most products.

• benefit :

(1) Significantly improve test quality;

(2) Continuously optimize testing costs;

(3) Testing capacity is autonomous and controllable.

As mentioned above, on the one hand, chip testing requires seeking a balance between "yield, quality, and cost", which is an art of balance; on the other hand, chip testing is also a guarantee of product quality and a "quality guard" of the semiconductor industry chain. At present, there is still a large gap between the performance of domestic testing equipment and the quality of testing factories and international industry leaders, and engineers and managers have a long way to go. However, under the general trend of rapid development of China's semiconductor industry, China's chip testing industry is booming and has broad prospects. Moore's Elite Testing Service is also seeking a better balance between "yield, quality, and cost" to protect the quality of China's chip products.

Scan the QR code to add WeChat and submit test requirements