[Shishuo Design] Bypass capacitors and coupling capacitors: Stabilizing voltage the right way
Bypass capacitors are often required during the development of electronic products. Figure 1 shows a switching regulator that generates a low voltage from a high voltage. In this type of circuit, the bypass capacitor ( C BYP ) is particularly important. It must support switching currents on the input path so that the supply voltage is stable enough to support device operation.
Figure 1. ADP2441 switching regulator with bypass capacitor C BYP at the input .
Because the input capacitance in the buck converter is part of the critical path (hot loop) of this topology, the C BYP connection must ensure as little parasitic inductance as possible. Therefore, the installation location of this component is crucial. The left side of Figure 2 shows a less-than-good layout. The traces connected to the bypass capacitors are thin. The current flowing into the voltage converter does not flow directly from the bypass capacitor. The bypass capacitor only touches the main circuit slightly. This increases the parasitic inductance produced by the capacitor and reduces the effectiveness of this component. It is recommended to use the layout shown on the right side of Figure 2. The efficiency of the bypass capacitor is very high. The connection itself creates only a very small amount of parasitic inductance. It can also be seen from the figure that the pin assignment of a converter (such as a switching regulator) has an impact on the board layout. As you can see from the right side of Figure 2, the V IN and GND pins are very close to each other, closer than the not so good layout on the left. This results in a smaller loop area between the bypass capacitor and the integrated circuit.
Figure 2. A bypass capacitor connected in an unfavorable manner (left) and a bypass capacitor connected in a favorable manner (right).
Because the bypass capacitor should be connected with as little parasitic inductance as possible, it is recommended to place the bypass capacitor on the same side of the board as the switching regulator. However, in some applications, the switching regulator on the front side can only be decoupled with the bypass capacitor at the bottom of the board. This is the case when there is not enough space for a larger decoupling capacitor. In this case, vias are used to connect the capacitors. Unfortunately, vias can create several nanohenries of parasitic inductance. In order to minimize the impedance of this connection, various connection suggestions have been proposed, as shown in Figure 3.
Figure 3. When the bypass capacitor is connected to a through hole, there are several connection options.
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Version A is not very advantageous. In this option, a thin trace is used between the via and the bypass capacitor. Depending on where the supporting trace runs on the other side of the board, this layout arrangement may also result in increased parasitic inductance.
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In version B , the via is located closer to the bypass capacitor, so this connection is more advantageous. Additionally, two vias are used in parallel. This reduces the overall inductance of the entire connection.
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Version C is more advantageous, where the connected loop area is very small, so only a minimal amount of parasitic inductance is produced. However, because the bypass capacitor is so small and the cost of the manufacturing process is low, it is not possible or impossible to create a via underneath the component.
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Version D provides a very interesting connection. Depending on how a particular ceramic bypass capacitor is designed, the parasitic inductance created by the lateral connection to the circuit board may be minimal.
For these components to achieve high efficiency, the location of the bypass capacitor on the circuit board is critical. That is, it is important to use the connection with the lowest possible parasitic inductance. Proper connections should be made using the same side of the board as the circuit, as shown in Figure 2. In some special cases, it may be necessary to connect the bypass capacitor to the back of the board, in which case the connection with the lowest possible parasitic inductance should be chosen as shown in versions B, C, and D of Figure 3.
Original text reproduced from Analog Devices
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