Inverting adder schematic and circuit diagram

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Inverting adder schematic and circuit diagram [Copy link]

1. What is an adder?
　　An adder is used to perform addition.
　　It is a device that generates the sum of numbers. A device that takes the addend and the augend as input and the sum and the carry as output is a half adder. If the addend, the augend and the carry in the lower digit are inputs, and the sum and the carry are outputs, it is a full adder. It is often used as a computer arithmetic logic unit to perform logical operations, shifts and instruction calls.
　　

　　For 1-bit binary addition, there are five related quantities: 1, addend A, 2, addend B, 3, the carry of the previous bit CIN, 4, the sum S of the two numbers at this bit, 5, the carry COUT generated by the addition of the two numbers at this bit. The first three quantities are input quantities, and the last two quantities are output quantities. All five quantities are 1 bit.
　　For 32-bit binary addition, there are also five related quantities: 1, addend A (32 bits), 2, addend B (32 bits), 3, the carry of the previous bit CIN (1 bit

4, the sum S (32 bits) of the two numbers added at this digit, 5, the carry COUT (1 bit) generated by the addition of the two numbers at this digit.
　　To implement 32-bit binary addition, a natural idea is to repeat the 1-bit binary addition 32 times (i.e., a bit-by-bit carry adder). This is undoubtedly feasible and easy to do, but since the CIN of each bit is provided by the COUT of the previous bit, the second bit must be calculated after the result of the first bit is calculated before it can start calculating; the third bit must be calculated after the result of the second bit is calculated before it can start calculating, and so on. The final 32nd bit must be calculated after all the results of the first 31 bits are calculated before it can start calculating. This method makes the time required to implement 32-bit binary addition 32 times the time required to implement 1-bit binary addition.
　　Basic method
　　It can be seen that the above method performs the 32-bit addition serially one bit at a time. To shorten the time, we should try to parallelize the above process.
　　Type
　

　　For the unit adder, there are two basic types: half adder and full adder.
　　Half adder has two inputs and two outputs. The inputs can be labeled A, B or X, Y, and the outputs are usually labeled S and C. A and B are S after XOR operation and C after AND operation.
　　Full adder introduces the input of base value to calculate larger numbers. To distinguish the two base lines of the full adder, the input is marked as Ci or Cin, and the output is marked as Co or Cout. Half adder is abbreviated as HA and full adder is abbreviated as FA.
　　Half adder: Circuit diagram of half adder Half adder has two binary inputs, which adds the input values and outputs the result to the sum (Sum) and the base (Carry). Although half adder can generate base values, half adder itself cannot process base values.
　　Full adder: Full adder has three binary inputs, one of which is a base value input, so full adder can process base values. A full adder can be made up of two half adders.
　　Note that the last OR gate at the binary output can also be replaced by an XOR gate without changing the rest of the parts. This is because the OR gate and the XOR gate differ only when the inputs are all 1, and this possibility no longer exists.
　　2. Adder Principle
　　Suppose the i-th input of an n-bit adder is ai, bi, ci, and the outputs are si and ci+1, where ci is the carry from the lower bit, ci+1 (i=n-1, n-2, ..., 1, 0) is the carry to the higher bit, c0 is the carry input of the entire adder, and cn is the carry output of the entire adder. Then and
　

　　si=aiii+ibii+iici+aibici, (1) carry ci+1=aibi+aici+bici, (2)
　　let gi=aibi, (3)
　　pi=ai+bi, (4)
　　then ci+1= gi+pici, (5)
　　as long as aibi=1, a carry to the i+1 position will be generated, and g is called the carry generation function; similarly, as long as ai+bi=1, ci will be transferred to the i+1 position, so p is called the carry transfer function. Expanding equation (5), we get: ci+1= gi+ pigi-1+pipi-1gi-2+…+ pipi-1…p1g0+ pipi-1…p0c0(6).
　　As the number of bits increases, equation (6) will become longer, but the depth of three logic levels is always maintained, so the delay of forming a carry is a constant that is independent of the number of bits. Once the carry (c1~cn-1) is calculated, the sum can be obtained from equation (1).
　　The adder that uses the above formula to generate all carries in parallel is a carry-lookahead adder. One gate delay is required to generate gi and pi, two gate delays are required for ci, and two gate delays are required for si, for a total of five gate delays. Compared with the series adder (generally 2n gate delays), the delay time of the carry-lookahead adder is greatly shortened (especially when n is relatively large).
　　3. Inverting adder equivalent schematic diagram
　　The inverting adder circuit, also known as the inverting summing circuit, refers to more than one input signal entering the inverting input terminal, and the output result is the absolute value of the sum of multiple signals (voltage polarity is opposite). As shown in the circuit a in the figure, when R1=R2=R3=R4, its output voltage = the absolute value of IN1+IN2+IN3, that is, it constitutes an inverting adder circuit. When R4>R1, the circuit also has the function of signal amplification.
　

　　Figure Inverting adder and principle equivalent diagram
　　The basic circuit structure of the inverting adder is an inverting amplifier. From its "virtual ground" characteristics, it can be seen that both input terminals are at 0V ground potential. This determines the control purpose of the circuit, which is to make the potential of the inverting input terminal 0V (the target value of the non-inverting input terminal is 0V). Taking the circuit parameters and input signal values of the circuit in Figure a as an example for analysis, the equivalent diagram shown in Figure b above can be obtained. The bias circuit of the inverting adder is still a series voltage division circuit overall, but the circuit principle of resistor parallel shunt is involved in the input circuit, and the equation can be listed: IR4=IR1+IR2+IR3. The "secret" of the inverting adder is thus revealed.
　　Since the inverting input terminal is at the ground potential of 0V, when the input signal IN3=0V, no signal current is generated in this branch, which is equivalent to no signal input, thus becoming IN1+IN2=-OUT. When IR1 (1V/10k) = 0.1mA, IR2 (1V/10k) = 0.1mA, only when the OUT output is -2V, the condition of IR4 = IR1 + IR2 is satisfied.
　　If the principle equivalent diagram is further simplified (see circuit c in the figure), a very familiar figure will come into our mind: Isn't this an inverting amplifier circuit? Yes, that's right, the inverting summation (inverting adder) circuit is an inverting (including amplification and attenuation) device. In practical
　　applications, due to the obvious defects of the in-phase adder, due to the extremely high input impedance, the signal input current can only form a loop through multiple IN terminals (which will cause the input signal voltage to be involved and change, resulting in large calculation errors). Unless the internal resistance of various IN signal sources is very small, it will not affect the calculation accuracy. Therefore, it is less used. The inverting summing circuit has a very low input impedance due to its "virtual ground" characteristics, which allows the input currents of various signals to enter the input terminal in a "convergence mode" and does not cause current flow between the input signals. Therefore, it can ensure the calculation accuracy and is widely used
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