Common RF transceiver structure

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Common RF transceiver structure [Copy link]

Transceivers with excellent performance in communication systems usually have advantages such as high gain, good selectivity, and high isolation. Commonly used RF transceiver structures usually include three architectures: superheterodyne transceiver, zero intermediate frequency transceiver, and digital intermediate frequency transceiver.
Superheterodyne transceiver
The block diagram of the superheterodyne transceiver architecture is shown in Figure 1. The superheterodyne transceiver is the most commonly used transceiver architecture. It usually uses one or two frequency conversions to convert the RF frequency to the required intermediate frequency, or convert the intermediate frequency to the required RF frequency. The superheterodyne transceiver can flexibly select the appropriate intermediate frequency to enhance the system's anti-interference ability, and can allocate link gain and filters through multiple frequency conversions, with multiple frequency points, making the link gain allocation more reasonable and obtaining excellent selectivity, sensitivity and dynamic range. However, the superheterodyne transceiver also has some disadvantages: such as complex structure that is not conducive to integration, difficult to suppress image frequencies, more components used, high cost, and usually multiple frequency conversions. The nonlinear characteristics of the mixer will lead to more interference frequencies.

Figure 1 Superheterodyne transceiver architecture
Zero IF transceiver
The block diagram of the zero IF transceiver architecture is shown in Figure 2. Figure 2 Zero IF transceiver The zero IF transceiver only needs to undergo one frequency conversion and does not have components such as IF amplifiers and IF filters. Therefore, the architecture is simple and the cost is low. The link gain can be distributed to the RF and baseband parts. An ideal zero IF transceiver will not produce intermodulation products, and since the difference frequency of the mixer is zero, there is no problem of image interference, which reduces the difficulty of filter design. It does not require a high-performance filter to achieve a good level of link spurious suppression capability. DC deviation, I/Q mismatch, and flicker noise are the disadvantages of the zero IF transceiver architecture.

Figure 2 Zero IF transceiver
Digital IF transceiver
In recent years, the rapid development of ADC and DAC has laid the foundation for the application of digital IF transceivers. Digital IF technology mainly includes bandpass sampling, sampling rate conversion, sampling or interpolation filtering, digital orthogonal modulation and demodulation, etc. The digital IF transceiver architecture block diagram is shown in Figure 2-3. The digital IF transceiver adopts the method of directly sampling the IF signal, and then completes the functions of down-conversion, channelization, clock recovery, demodulation, etc. in the digital signal part. Compared with the superheterodyne transceiver, fewer analog devices are used, which reduces the possibility of I/Q mismatch and has stronger anti-interference ability. With the continuous improvement of the resolution and accuracy of A/D and D/A chips, the digital IF frequency that can be directly processed will become higher and higher, which will help to reduce the pressure of RF transceiver front-end design. Digital IF transceivers also have the following disadvantages: In order to increase the frequency of digital IF, ADC and DAC need to have higher sampling rate and higher resolution, which will increase the cost of transceivers; however, if the ADC sampling frequency becomes higher, the signal-to-noise ratio will be deteriorated accordingly, which will seriously affect the performance indicators of the communication system.

Figure 3 Digital IF transceiver
Sliding IF receiver
The sliding IF receiver is a special superheterodyne receiver architecture. As shown in Figure 4, this type of receiver system still uses a double frequency conversion structure. Unlike the traditional superheterodyne structure, the local oscillator signals of the double frequency conversion are correlated, that is, the two local oscillator signals are obtained by multiplying or dividing a frequency source. The advantage of the sliding IF receiver is that it only requires one on-chip frequency synthesizer, which greatly reduces the complexity of the system and avoids the mutual traction between two irrelevant frequency synthesizers.

Figure 4 Sliding IF receiver system architecture
Frequency synthesis technology
Frequency sources have always played an important role in communication radar and other systems. Early frequency synthesis technology was directly synthesized by some crystal oscillators. With the continuous improvement of technology, PLL frequency synthesizers appeared later, using PLL technology to obtain the required frequency. With the development of the times, digital frequency synthesis technology has also gradually emerged. Nowadays, frequency synthesizers are widely used in communication radar systems, medical equipment and other aspects. The main implementation methods of frequency synthesis technology are: direct analog frequency synthesis technology (DS); phase-locked loop frequency synthesis technology (PLL); direct digital frequency synthesis technology (DDS); hybrid frequency synthesis technology, etc. The various technical indicators of the frequency source have an important impact on the performance of the frequency source. Direct analog frequency synthesis technology
Direct
analog frequency synthesis (DS) technology generates a large number of discrete frequencies through frequency multiplication, mixing and other processing, and then controls the output of the required frequency through switches. The architecture block diagram of direct analog frequency synthesis technology is shown in Figure 5. After the reference frequency source is processed by frequency multiplication, mixing and other processing, the generated discrete signal is output after passing through the switch filter component. Figure 5 Direct analog frequency synthesis architecture diagram Direct analog frequency synthesis technology has a short frequency conversion time, is easy to generate high frequencies, and has good indicators such as phase noise. However, due to the use of a large number of components, the frequency synthesizer is difficult to integrate, the cost is high, and it is easy to generate a large number of spurious components. Therefore, the spurious suppression capability of the frequency synthesizer usually depends on the performance of the filter.

Figure 5 Direct analog frequency synthesis architecture diagram Phase
-locked frequency synthesis technology
Around 1965, phase-locked frequency synthesis (PLL) technology appeared. The phase-locked loop mainly includes phase detector (PFD), charge pump (CP), loop filter (LPF), voltage-controlled oscillator (VCO), divider and other devices. PLL technology is mainly based on the principle of closed-loop negative feedback. The PFD is used to compare the phase of the reference clock signal with the phase-detection clock signal, and then the phase-detection result is sent to the charge pump. After LPF filtering, the phase error voltage is used to control the VCO to change the clock signal frequency. Due to the negative feedback mechanism, as long as there is a changing phase difference between the two signals, the oscillation frequency of the VCO will keep changing. When the phase-locked loop is locked, the phase difference is a fixed value, and the error voltage no longer changes. At this time, the loop enters the locked state, that is, the synchronization of the input and output signals is achieved. Its architecture block diagram is shown in Figure 6.

Figure 6 PLL principle block diagram
PLL technology outputs signal with good phase noise, high frequency stability, strong spurious suppression capability, and avoids the use of a large number of filters. However, it still has its own shortcomings: for example, the frequency conversion time is long, the frequency resolution is not high, and a voltage-controlled oscillator with good performance can improve the frequency stability, but it also introduces new noise.
Direct digital frequency synthesis technology
Direct digital frequency synthesis (DDS) technology dates back to the last century. In 1971, American scholars J. Tierney, CM Rader, and B. Gold proposed the idea of DDS, but it was not taken seriously due to the technical conditions at the time. The DDS architecture block diagram is shown in Figure 2-7. Figure 7 DDS architecture block diagram DDS frequency synthesis technology is a fully digital frequency synthesis technology. The phase accumulator serves as the address generator of the ROM and contains samples of the synthesis function. The multi-stage phase accumulator of the digital frequency synthesizer forms a cyclic phase code, and then compares the phase sample with the synthesized oscillation amplitude sample, and outputs the required signal after processing by the DAC and low-pass filter. DDS technology has the advantages of high frequency resolution, fast frequency switching time, high frequency tuning rate, good phase continuity during frequency hopping, and convenient control using digital interface, but it also has disadvantages such as the maximum frequency of the synthesized signal is not high enough, the amplitude noise level is relatively high, and there are many spurious components. These factors limit the application field of DDS. At present, the development of DDS is mainly to develop as a whole within the framework of a known block diagram, with faster operation speed and lower energy consumption and cost.

Figure 7 DDS architecture block diagram
DDS and PLL hybrid frequency synthesis technology
DDS and PLL hybrid frequency synthesis technology has multiple implementation methods, among which the direct method and mixing method are commonly used. Direct hybrid frequency synthesis technology uses DDS directly as the reference source of PLL to drive PLL to generate the required frequency. It has a simple structure and is easy to design, but the frequency switching time is still limited by the loop filter in PLL. It is necessary to find the optimal loop bandwidth to make the frequency switching time and phase noise reach the ideal value, as shown in Figure 8.

Figure 8 Direct hybrid frequency synthesis technology block diagram
The mixing method is divided into in-loop mixing and out-loop mixing. The principle block diagram of the in-loop mixing frequency synthesizer is shown in Figure 9.

Figure 9 Principle block diagram of DDS+PLL in-loop mixing frequency synthesizer.
The design structure of DDS and PLL in-loop mixing has lower phase noise and reference excitation, but this architecture increases the requirements for the performance of the bandpass filter. Compared with the in-loop mixing, the main difference between DDS+PLL out-loop mixing and in-loop mixing is the different mixing positions. This structure has excellent bit noise, high resolution, and fast frequency switching speed, but the intermodulation components generated are difficult to suppress, which affects the application prospects, as shown in Figure 10.

Figure 10 Principle block diagram of DDS+PLL out-of-loop mixing frequency synthesizer