[Shishuo Design] How to balance low power consumption and high precision? Make good use of the "disable pin" of the op amp

If the op amp needs to be used as a buffer amplifier for an ADC, as shown in Figure 1, it must be active to perform its function. However, power consumption can still be kept low if the amplifier is switched to shutdown mode via the disable pin. Typically, shutdown mode is used whenever the ADC does not need to read any new values ​​into its sample and hold block.

Figure 1. ADC driver and reference buffer.

Typical schematic of an ADC input stage.

The simplest way to implement this is through the conversion start command. In a standard ADC, the input (sample and hold) capacitors are first charged to the value to be measured. This is done before the signal is sent to the ADC for conversion. The input capacitors are then isolated and connected to the input of the converter stage, and the conversion begins. The conversion is then completed and the done signal is set, depending on the converter type. Now the real question is: when does the op amp have to be active? The amplifier must be active long enough ahead of the conversion start signal to ensure that the internal input capacitors have the same value as the signal being measured. How long this takes depends on factors such as the size of the input capacitors, the size of the voltage being measured, and the rate at which the op amp can drive a capacitive load.

The data sheet for the ADC (AD7980) gives an input capacitance of 30pF with a series impedance of 400Ω. However, op amps are not that simple. The parameter table lists the capacitive load as 15pF, but it can be higher, see the corresponding graph (Figure 2). Also consider the case of using a low-pass filter of 2.7nF and 20Ω.

Figure 2. Frequency response of the ADA4807.

This graph shows that the module can drive sufficiently high capacitive loads. After being disabled, the amplifier requires approximately 500ns to reach the full-scale output level, which in this case is a maximum of 5V or 4.096V.

To be safe, we assume the amplifier is turned on 750ns before the start of the conversion. Compare the estimated data from 1kSPS to 1MSPS.

At 1kSPS, the potential power savings is 99.83% (0.02mW total), and at 1MSPS, 92.41% (10.75mW total). This is just the power savings for the ADC driver; the reference buffer also saves power.

This example is intended to illustrate the capabilities of modern devices. At a minimum sampling time of 500ns, the SINAD deviation is less than 0.5dB. For drivers, there are faster related devices that need to be looked at and used flexibly. We have only considered applications where they are used as buffers (gain = 1). For inverting or other amplifiers, the power savings will also vary. Further analysis is required through measurements.