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To meet your stringent needs, this PLL has the highest performance!

Latest update time:2020-04-19
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With the increasing demand for frequency bandwidth, throughput and dynamic range of communication systems, and the requirement for millimeter wave 5G to use higher antenna frequencies, higher requirements are placed on the quality of the local oscillator (LO) or clock used in communication systems or mixed signal systems, respectively.


The ADF4371 phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) and the similar ADF4372 fully demonstrate ADI's efforts to meet these demanding application requirements.


Figure 1. ADF4371 block diagram.


Frequency coverage


To maximize the frequency coverage, the ADF4371/ADF4372 VCO covers an octave range of 4 GHz to 8 GHz. In addition, by using a divider at the output, 1/2/4/8/16/32/64 divisions can be performed to achieve full frequency coverage between 62.5 MHz and 8000 MHz at the main output RF8. At the same time, an identical second output is provided to support the user to drive the converter clock. For an 8 GHz output frequency, the open-loop phase noise of the VCO is –109 dBc/Hz at a 100 kHz offset.


Until recently, generating high frequencies required the use of external frequency multipliers, which are typically fabricated using GaAs processes and often require additional filtering and amplification to address the filtering issues.


To achieve higher frequencies, the ADF4371/ADF4372 integrates a frequency doubler that provides an 8 GHz to 16 GHz output through the differential pin RF16. The ADF4371 also has a frequency quadrupler that generates a 16 GHz to 32 GHz output at the differential output RF32. To minimize the generated frequency doubler noise, the ADF4371/ADF4372 has built-in tracking filters to optimize the power level to achieve the desired frequency while suppressing the frequency doubler noise. At the doubled frequency output, the VCO feedthrough noise is –45 dBc. At the quadrupled frequency output, the noise is suppressed to approximately –35 dBc.


Excellent PLL performance for converter clock applications


Improvements to the PLL circuitry mean that the ADF4371/ADF4372 products can have a PLL quality factor as low as –234 dBc/Hz, which, combined with a low 1/f noise of –127 dBc/Hz (at 1 GHz nominal output frequency, 10 kHz offset), allows the user to achieve clocks with as little as 40 fsrms jitter (1 kHz to 100 MHz integration range), making them ideal for demanding converter clock applications. To minimize the potential for resistor noise in the loop, a simple low-pass filter is recommended with small resistor values. To achieve the low noise goal, a high frequency (250 MHz, or 125 MHz when the reference frequency multiplier is enabled) ultra-low noise reference source must be used. For integer-N applications, the maximum operating frequency of the phase frequency detector (PFD) can be up to 250 MHz. The multiplied VCO differential output, RF16, can be directly connected to some ADI converters without the need for external balun circuitry that would increase cost and performance. There is no performance degradation from 6.144 GHz to 12.288 GHz.


Figure 2. RMS jitter at 6.144 GHz.


Communications and Instrumentation LO


For wireless and instrumentation applications, the ADF4371/ADF4372 has a built-in 39-bit resolution ∑-∆ modulator that can achieve submillihertz resolution with 0Hz frequency error. In this case, the ADF4371 PFD can run at a maximum PFD frequency of 160 MHz. In these applications, the ADF4371/ADF4372 provides < 48 fs rms jitter. The ADF4371 also has industry-leading PLL spurious performance, with PFD spurs as low as –100 dBc and unfiltered integer boundary spurs as low as –55 dBc. This level of performance greatly simplifies frequency planning and reduces time to market. Many fractional-N PLL and VCO devices use unprecedented fractional-N spurious mechanisms, which lead to additional unknown characteristics and frequency planning work, thereby increasing complexity and cost.


Figure 3. RMS jitter at 12.288 GHz.


Small size


The ADF4371/ADF4372 PLL/VCO devices are available in a 7 mm × 7 mm, 48-lead land grid array (LGA) package. Minimal additional decoupling is required, so excellent performance can be achieved using a small solution size.


For best performance, it is recommended to use a good quality low dropout (LDO) regulator such as the ADM7150 or LT3045. The VCO can be powered by either 3.3 V or 5 V, with the rest of the circuitry powered by a 3.3 V rail. The ADF4371 can be simulated using ADIsimPLL™ to help the user design the appropriate external component circuitry needed to implement the entire PLL system.


in conclusion


The ADF4371 delivers industry-leading frequency coverage, performance, and small size to meet the high demands of new communications and instrumentation systems.

ADF4371


  • RF output frequency range: 62.5 MHz to 32,000 MHz

  • Fractional-N and Integer-N Synthesizers

  • High resolution 39-bit fractional modulus

  • Typical Phase Frequency Detector (PFD) Spurious: -90 dBc (typical)

  • Integrated RMS jitter < 40 fs (1 kHz – 100 MHz)

  • Normalized Phase Noise Floor (FOM) -234 dBc/Hz

  • Phase Frequency Detector (PFD) operating up to 250 MHz

  • Reference frequency up to 600 MHz

  • Low Phase Noise, Voltage Controlled Oscillator (VCO)

  • Programmable 1, 2, 4, 8, 16, 32 or 64 divide-by-64 outputs

  • 0.06 -8 GHz Output (RF8)

  • 0.06 -8 GHz Output (RFAUX8)

  • 8 -16 GHz Output (RF16)

  • 16 -32 GHz output (RF32)

  • Locking time ~3ms, with automatic calibration function

  • Lock time <20us, with calibration bypass function

  • Analog and digital power supply: 3.3 V

  • VCO supply voltage: 3.3 V and +5 V.

  • Programmable output power levels

  • RF output mute function

  • 7mm × 7mm 48-pin LGA package

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