Practical information | Analyzing CAN communication on STM32 from head to toe

1. Working mode Control INRQ and SLEEP through CAN_MCR register
1. Initialization INRQ=1 SLEEP=0
Software initialization should be done in hardware
2. Normal INRQ=0 SLEEP=0
After initialization, the software should let the hardware enter normal mode so as to receive and send messages normally
3. Sleep SLEEP=1 bxCAN can work in low power sleep mode

2. Test mode controls LBKM and SILM through the CAN_BTR register
1. Silence can be accepted but not sent

2. Loop can send but not receive
3. Loop silence can only send and receive

3. Debug mode

In the CAN protocol, the identifier of the message does not represent the address of the node, but is related to the priority of the message. Therefore, when the node receives the message, it decides whether the software needs the message based on the value of the identifier; if it does, it copies it to the SRAM; if it does not, the message is discarded without software intervention. To meet this demand, bxCAN provides 14 variable-width, configurable filter groups (13~0) for the application to receive only those messages required by the software. Hardware filtering saves CPU overhead, otherwise it must be filtered by software, which will occupy a certain amount of CPU overhead.

The CAN of the STM32 ordinary chip has 14 filter groups (the interconnected type has 28 filter groups) to filter the received frames. Each filter group includes 2 configurable 32-bit registers: CAN_FxR1 and CAN_FxR2. For the filter group, by setting the FBMx bit of CAN_FM0R,
1. Mask bit mode
In this way, the identifier match value is stored in CAN_FxR0, and the mask code is stored in CAN_FxR2. That is, if a bit in CAN_FxR2 is 1, the corresponding bit in CAN_FxR1 must match the corresponding bit in the identifier of the received frame to pass the filter. The bit in CAN_FxR2 that is 0 indicates that the corresponding bit in CAN_FxR1 does not need to match the received frame.

2. Identifier list mode
At this time, both CAN_FxR1 and CAN_FxR2 are identifiers to be matched, and the identifier of the received frame must match one of them to pass the filter.

Understanding: The identifier list mode is used to filter out an identifier, while the mask bit mode can filter out a group of identifiers because some bits are masked. The filter group that is not needed should be disabled.

Generally, we use ordinary types, so in this article we can say that STM32 has 14 filter groups. Depending on the configuration, each filter group can have 1, 2 or 4 filters. These filters are equivalent to checkpoints. Whenever a message is received, CAN must first "pass" the received message through these filters. The messages that can pass are valid messages and are collected into FIFO. The invalid messages that cannot pass are invalid messages (not sent to "me") and are directly discarded. The number of filters can be selected by changing the values ​​of two configurable registers. In a group of filters, the entire group of filters uses the same working mode.

In addition, the filter width in each filter group is variable and can be 32 bits or 16 bits. According to the working mode and width, a filter group can become one of the following forms:

All filters are connected in parallel, that is, a message is considered valid as long as it passes one filter. Each filter group has two 32-bit registers for storing the "standard values" for filtering, namely FxR1 and FxR2.

Interpretation:
1. In 32-bit mask bit mode:
There is 1 filter.
FxR2 is used to specify which bits need to be concerned, and FxR1 is used to specify the standard value of these bits.

2. In 32-bit list mode:

There are two filters.
FxR1 specifies the standard value of filter 0. The received message is considered to pass only if its identifier is exactly the same as FxR1.

FxR2 specifies the standard value for filter 1.

3. In 16-bit mask bit mode:
There are 2 filters.
FxR1 configures filter 0, where bits [31-16] specify the bits to be concerned about and bits [15-0] specify the standard values ​​of these bits.

FxR2 configures filter 1, where bits [31-16] specify the bits of interest and bits [15-0] specify the standard values ​​for those bits.

4. In 16-bit list mode:
There are 4 filters.
Bits [15-0] of FxR1 configure filter 0, bits [31-16] of FxR1 configure filter 1.
Bits [15-0] of FxR2 configure filter 2, bits [31-16] of FxR2 configure filter 3.

The STM32 CAN has two FIFOs, FIFO0 and FIFO1. For easy distinction, FIFO0 is written as FIFO_0 and FIFO1 is written as FIFO_1.

Each filter group must be associated with and can only be associated with one FIFO. The default reset is associated with FIFO_0. The so-called "association" means that if the received message passes through a filter, the message will be stored in the FIFO connected to the filter. On the other hand, each FIFO is associated with a series of filter groups, and the two FIFOs just divide all the filter groups. Whenever a message is received, CAN compares the message with the filter associated with FIFO_0. If it matches, the message is placed in FIFO_0. If it does not match, the message is compared with the filter associated with FIFO_1. If it matches, the message is placed in FIFO_1. If it still does not match, the message is discarded.

All filters of each FIFO are connected in parallel. As long as a message passes any one of the filters, it is valid. If a message meets the requirements of both FIFO_0 and FIFO_1, it will obviously only be placed in FIFO_0 according to the operation order.

Only activated filters in each FIFO work. In other words, if a FIFO has 20 filters, but only 5 are activated, then when comparing messages, only these 5 filters are compared. Generally, when a filter is to be used, it is directly activated during the initialization phase. It should be noted that each FIFO must activate at least one filter before it can receive messages. If no filter is activated, all messages are discarded. Generally, if you do not want to use complex filtering functions, the FIFO can only activate one set of filters and set it to a 32-bit mask bit mode, and both standard value registers (FxR1, FxR2) are set to 0. In this way, all messages can pass. (This is what is done in the routines provided by STM32!)

The filter number is used to speed up the CPU's processing of received messages. When a valid message is received, CAN will store the received message and the filter number it passed into the receiving mailbox. When the CPU processes the message, it can quickly know the purpose of the message based on the filter number and make corresponding processing.

It is actually possible to not use the filter number. At this time, the CPU needs to analyze the identifier of the received message to know the purpose of the message. Since the identifier contains more information, the processing is slower.

The STM32 uses the following rules to number filters:

This way, each filter has its own number in the FIFO.

In FIFO_0, the numbering starts from 0 – (M-1), where M is the total number of its filters.

In FIFO_1, the numbering starts from 0 – (N-1), where N is the total number of its filters.

If a FIFO has many filters, there may be a message that can pass through several filters. At this time, where does this message come from?
When using filters, STM32 filters in the following order:

In this order, the first filter that the message can pass through is the filter number of the message and is stored in the receiving mailbox.

The above example illustrates the filter rules of bxCAN: when receiving a message, its identifier is first compared with the filter configured in the identifier list mode; if it matches, the message is stored in the associated FIFO, and the sequence number of the matched filter is stored in the filter match sequence number. As shown in the example, the message identifier matches the #4 identifier, so the message content and FMI4 are stored in the FIFO. If there is no match, the message identifier is then compared with the filter configured in the mask bit mode. If the message identifier does not match any identifier in the filter, the hardware discards the message without any disturbance to the software.

The process of sending a message

The application selects an empty send mailbox; sets the identifier, data length and data to be sent; then sets the TXRQ position of the CAN_TIxR register to '1' to request sending. After the TXRQ position is '1', the mailbox is no longer an empty mailbox; and once the mailbox is no longer empty, the software no longer has write permission to the mailbox register. After the TXRQ position is 1, the mailbox immediately enters the waiting state and waits to become the highest priority mailbox, see the sending priority. Once the mailbox becomes the highest priority mailbox, its state changes to the scheduled sending state. Once the CAN bus enters the idle state, the message in the scheduled sending mailbox is immediately sent (enters the sending state). Once the message in the mailbox is successfully sent, it immediately becomes an empty mailbox; the hardware accordingly sets the RQCP and TXOK positions of the CAN_TSR register to 1 to indicate a successful transmission. If the transmission fails, the ALST position of the CAN_TSR register is set to '1' due to arbitration, and the TERR position is set to '1' due to a transmission error.

Sending priority

1. Identifier Determination
When there are more than one mailboxes registered for sending, the order of sending is determined by the identifier of the message in the mailbox. According to the CAN protocol, the message with the lowest identifier value has the highest priority. If the identifier values ​​are equal, the message with the smaller mailbox number is sent first. It is determined by the order of sending requests.

2. Determined by the order of transmit requests
By setting the TXFP position of the CAN_MCR register to '1', the transmit mailbox can be configured as a transmit FIFO. In this mode, the priority of the transmit is determined by the order of the transmit requests. This mode is useful for segmented transmission.

Abort
The send request can be aborted by setting the ABRQ bit of the CAN_TSR register to '1'. If the mailbox is in the waiting or scheduled state, the send request is aborted immediately. If the mailbox is in the sending state, then the abort request may lead to two results. If the message in the mailbox is successfully sent, the mailbox becomes an empty mailbox, and the TXOK bit of the CAN_TSR register is set to '1' by hardware. If the message in the mailbox fails to be sent, the mailbox becomes the scheduled state, and then the send request is aborted, the mailbox becomes an empty mailbox and the TXOK bit is cleared to '0' by hardware. Therefore, if the mailbox is in the sending state, the mailbox will become an empty mailbox after the sending operation is completed.

The receiving process
FIFO starts from the empty state. After receiving the first valid message, the FIFO state changes to pending_1, and the hardware sets FMP[1:0] of the CAN_RFR register to '01' (binary 01b). The software can read the FIFO output mailbox to read the message in the mailbox, and then release the mailbox by setting the RFOM bit of the CAN_RFR register to '1', so that the FIFO becomes empty again. If a valid message is received while the mailbox is released, the FIFO remains in the pending_1 state, and the software can read the FIFO output mailbox to read the newly received message. If the application does not release the mailbox, after receiving the next valid message, the FIFO state changes to pending_2 (pending_2), and the hardware sets FMP[1:0] to '10' (binary 10b). Repeating the above process, the third valid message changes the FIFO to pending_3 state (FMP[1:0]＝11b). At this time, the software must set the RFOM bit to 1 to release the mailbox so that the FIFO can have space to store the next valid message; otherwise, the arrival of the next valid message will result in the loss of a message.

When the FIFO is in the register_3 state (i.e. all three mailboxes of the FIFO are full), the next valid message will cause an overflow and a message will be lost. At this point, the hardware sets the FOVR bit of the CAN_RFR register to '1' to indicate the overflow. Which message will be discarded depends on the settings of the FIFO:

Once a message is stored in the FIFO, the hardware will update the FMP[1:0] bits and if the FMPIE bit in the CAN_IER register is '1', an interrupt request will be generated.

When the FIFO becomes full (ie the third message is stored), the FULL bit of the CAN_RFR register is set to '1', and if the FFIE bit of the CAN_IER register is '1', a full interrupt request is generated.

In case of overflow, the FOVR bit is set to '1' and if the FOVIE bit in the CAN_IER register is '1', an overflow interrupt request is generated.

The bit timing characteristic logic monitors the serial CAN bus by sampling and adjusts its sampling point by synchronizing with the edge of the frame start bit and by resynchronizing with the following edge.

Its operation can be simply explained as dividing the nominal bit time into 3 segments as follows:

Its value can be programmed from 1 to 16 time units, but can also be automatically extended to compensate for positive phase drift caused by frequency differences between different nodes in the network.

● Time Segment 2 (BS2): defines the location of the sending point. It represents PHASE_SEG2 in the CAN standard. Its value can be programmed from 1 to 8 time units, but can also be automatically shortened to compensate for negative phase drift.

The resynchronization jump width (SJW) defines the upper limit on how many time units can be extended or shortened in each bit. Its value can be programmed from 1 to 4 time units.

A valid transition is defined as the first transition from dominant to recessive when bxCAN itself does not send a recessive bit. If a valid transition is detected in time segment 1 (BS1) instead of in the synchronization segment (SYNC_SEG), the BS1 time is extended by up to SJW, so that the sampling point is delayed. On the contrary, if a valid transition is detected in time segment 2 (BS2) instead of in SYNC_SEG, the BS2 time is shortened by up to SJW, so that the sampling point is advanced. In order to avoid software programming errors, the setting of the bit time characteristic register (CAN_BTR) can only be performed when bxCAN is in the initialization state.

● Transmit interrupt can be generated by the following events:
─ Transmit mailbox 0 becomes empty, the RQCP0 bit of the CAN_TSR register is set to '1'.
─ Transmit mailbox 1 becomes empty, the RQCP1 bit of the CAN_TSR register is set to '1'.
─ Transmit mailbox 2 becomes empty, the RQCP2 bit of the CAN_TSR register is set to '1'.

● FIFO0 interrupt can be generated by the following events:
─ FIFO0 receives a new message, the FMP0 bit of the CAN_RF0R register is no longer '00'.
─ FIFO0 becomes full, the FULL0 bit of the CAN_RF0R register is set to '1'.
─ FIFO0 overflows, the FOVR0 bit of the CAN_RF0R register is set to '1'.

● FIFO1 interrupt can be generated :

─ When FIFO1 receives a new message, the FMP1 bit in the CAN_RF1R register is no longer '00'.
─ When FIFO1 becomes full, the FULL1 bit in the CAN_RF1R register is set to '1'.
─ When FIFO1 overflows, the FOVR1 bit in the CAN_RF1R register is set to '1'.

● Error and status change interrupts can be generated by the following events:
─ Error condition, refer to the CAN Error Status Register (CAN_ESR) for detailed information on error conditions.
─ Wake-up condition, monitoring the Start of Frame bit (SOF) on the CAN receive pin.
─ CAN enters sleep mode.

These two concepts are a bit difficult to understand. Let's take an example to understand. There are many doors in front of you, and different attributes are written on the doors. People have to enter the door according to the attributes, such as small door 1, small door 2, middle door, large door 1, and large door 2. Small door 1 requires people with a height of exactly 1.87 meters to enter, while the middle door requires people with a height less than 1.90 meters and greater than 1.87 meters to enter. These two concepts are the concepts of flag filters. One is a list of flags, and the other is a shielding bit. People who enter the door will have their height measured in the later stages. In order to quickly know their height, we can use the door they enter to represent it, because the door actually contains their height information. This is the concept of filter matching. Filter matching means that there are many doors that may allow this person to enter at the same time, but only the height of that door is closest to the person's height. For example, if a person is 1.70 meters tall, door A requires 1.68-1.12 meters, and door B requires 1.70 meters, then door B is selected. Door B is selected. The matching sequence number can directly know the person's height information.

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