Thorough analysis of the principle of capacitive decoupling

Latest update time：2024-02-22

Reads：

▲ For more exciting content, please click the blue words above to follow us!

Using capacitive decoupling is the main method to solve the problem of power supply noise. This method is very effective in improving the response speed of transient current and reducing the impedance of the power distribution system.

Capacitive decoupling is covered in many materials, but from different angles. Some are explained from the perspective of local charge storage (i.e. energy storage), some are explained from the perspective of the impedance of the power distribution system, and some explanations are more confusing. Sometimes they mention energy storage, and sometimes they mention impedance, so Many people feel a little confused when reading the information. In fact, these two formulations are essentially the same, but they look at the problem from different perspectives.

1. Explain the principle of capacitive decoupling from the perspective of energy storage.

When making a circuit board, a lot of capacitors are usually placed around the load chip, and these capacitors play a role in power decoupling. The principle can be illustrated in Figure 1.

(Formula 1)

As long as the capacitance C is large enough and only requires a small voltage change, the capacitor can provide a large enough current to meet the load transient current requirements. This ensures that the load chip voltage changes within the allowable range. Here, it is equivalent to the capacitor storing a part of the electrical energy in advance and releasing it when the load needs it. That is, the capacitor is an energy storage component. The existence of the energy storage capacitor allows the energy consumed by the load to be quickly replenished, thus ensuring that the voltage at both ends of the load does not change too much. At this time, the capacitor plays the role of a local power supply.

Understanding capacitors from the perspective of energy storage can easily lead to the illusion that the larger the capacitor, the better. And it is easy to mislead everyone into thinking that the energy storage effect occurs in the low frequency band and is not easy to expand to high frequencies. In fact, the function of any capacitor can be explained from the perspective of energy storage. Example below.

Figure 2 The role of capacitor energy storage extends to high frequencies

As shown in the figure above, assuming that in the low frequency band, such as tens of khz, since the inductive reactance generated by the low frequency signal on the inductor can be ignored, the ESL of the capacitor in the low frequency band can be approximately equal to 0. When the load requires a large current at an instant (tens of khz), the capacitor can supply power to the load through the ESR. The real-time nature of the power supply is very high. The ESR only consumes a part of the power, but does not affect the real-time nature of the power supply. Since the frequency is relatively low, the discharge time is also relatively long (the reciprocal of frequency), so the capacitor needs to have a larger capacity to discharge for a long time. Therefore, low-frequency energy storage is easy to understand.

For the same large capacitance, assuming that the frequency of load mutation is high (tens of Mhz or higher), when the load changes smoothly (tens of Mhz or higher), the inductive reactance formed on the ESL cannot be ignored. This inductive reactance A reverse electromotive force will be generated to prevent the capacitor from supplying power to the load, so the transient performance of the current actually obtained by the load is relatively poor, that is, the current of the capacitor cannot supply instantaneous current mutations. Although the capacitor has a large capacity, due to the large ESL , the large-capacity energy storage cannot play a role at this time. In fact, with a higher frequency, the time for the capacitor to supply power to the load is shortened (the reciprocal of the frequency), and the capacitor does not need to have such large energy storage. For high frequency, the key factor is ESL. To reduce the ESL of the capacitor, choose a small capacitor with a small package. The ESL will be significantly reduced. This is why we choose small capacitors for high frequency. In addition, the inductance introduced by the trace length will also be converted into ESL parameters, so the small capacitor must be close to the pin.

This understanding of energy storage can even be extended to pF-level capacitors. Theoretically, assuming there is no ESR, ESL and transmission impedance is 0, a large capacitor is fully capable of handling all frequencies. But this assumption does not exist. Therefore, a reasonable combination of large and small capacitors is required in the circuit to provide the ability to cope with loads at different frequencies. And the closer the capacitor is to the load, the smaller the impact of the equivalent inductance and resistance of the transmission line.

Figure 3 Cell phone Vbat power supply capacitor distribution diagram

For example, in the design of mobile phones, 47uf capacitors are hung on several branches of the vbat power supply branch. As shown in the picture above, 47uf capacitors are hung near the connector, near the PMU, and near the PA. It is believed that only the 47uf capacitors next to the PA have any effect on the PA. The effect is that the ones next to the connector and the ones next to the PMU have no effect on the PA. This is not the case in reality. When the PA requires instantaneous current, the three tantalum capacitors will supply power to the PA. The power supply process completely depends on the instantaneous voltage difference. Which capacitor is connected to the PA? The instantaneous voltage difference of the PA is the largest, which one supplies power more actively. The capacitance away from the PA needs to consider the impedance and inductive reactance of the transmission line. For low frequencies, this parasitic inductance can be ignored. For 217HZ, the total current required by the PA with three capacitors is far from enough. Therefore, when GSM power is high, the PA draws current from all three capacitors.

For low frequencies, the role of parasitic inductance can be ignored. The distance between these large capacitors and the chip is only reflected in the trace resistance. Generally, the voltage drop of the trace resistance of the power line is within 100 milliohms, which has very little impact on the charge and discharge of the capacitor, so it can be considered There is no need to place large capacitors very close to the chip on the motherboard.

Understanding power supply decoupling from the perspective of energy storage is very intuitive and easy to understand, but it is not very helpful for circuit design. Because it is difficult to consider from a quantitative perspective, it is suitable for qualitative analysis. Understanding capacitive decoupling from the perspective of impedance allows us to follow rules when designing circuits. In fact, when determining the decoupling capacitance of a power distribution system, the concept of impedance is used.

2. Understand the principle of decoupling from the perspective of impedance.

Remove the load chip in Figure 1, as shown in Figure 2. Looking to the left from point AB, the regulated power supply and capacitive decoupling system can be seen as a composite power supply system. The characteristic of this power supply system is that no matter how the load transient current changes between two points AB, the voltage between two points AB can be guaranteed to remain stable, that is, the voltage change between two points AB is very small.

Figure 4 Power supply part

We can use an equivalent power supply model to represent the above composite power supply system, as shown in Figure 3, a series model of a constant voltage source and internal resistance.

For this circuit the following equation can be written:

(Formula 2)

Assuming that the power supply is an ideal voltage source, that is, Z=0, and assuming that the impedance of the transmission path is also 0, then no matter how the load changes or how fast the change speed, the voltage source can react and ensure that both A and B The point voltage is always constant. But in fact, the internal resistance of the power supply is not zero, and the transmission line is not ideal, and these influencing factors are complex numbers and related to frequency, so the PDN impedance of the power supply appears.

Our ultimate design goal is to keep the voltage variation range between AB and AB very small no matter how the load transient current changes between AB and AB. According to Formula 2, this requirement is equivalent to the impedance Z of the power system being low enough. In Figure 4, we achieve this requirement through decoupling capacitors, so from an equivalent perspective, it can be said that the decoupling capacitors reduce the impedance of the power system. On the other hand, from the perspective of circuit principles, the same conclusion can be obtained. Capacitors exhibit low impedance characteristics for AC signals, so adding capacitors actually reduces the AC impedance of the power system.

Understanding capacitive decoupling from the perspective of impedance can bring great convenience to us in designing power distribution systems. In fact, the most fundamental principle of power distribution system design is to minimize impedance. The most effective design methods are guided by this principle.

In order to understand the concept of power supply output impedance (internal resistance), let us recall the definition of power supply internal resistance: when the load is disconnected and viewed from the load end, the constant voltage source is short-circuited and the cross-current source is open-circuited. As shown in Figure 6.

Figure 6 Equivalent diagram of internal resistance of power supply

It can be seen from Figure 6(b) that after connecting the capacitor in parallel, the internal resistance of the power supply changes when viewed from the load end, that is, Z'=Z//Z1, where Z1 is the capacitive reactance of the capacitor. It can be seen that the new internal resistance Z'<Z, so the change of the power supply at the power supply end decreases with the load, but Z' is a complex number, which is related to the frequency. The internal resistance is different at different frequencies. What the power supply PDN does is how to adjust the power supply at each frequency. The impedance under the segment should be as small as possible. Theoretically, by connecting countless capacitors in parallel, the internal resistance of the power supply can always be infinitely close to 0, so that the power supply is infinitely close to a cross-voltage source or a constant current source.

The capacitive reactance in Figure 6 cannot be simply calculated using jwC, because the capacitor is not an ideal model. It contains ESR and ESL, and these require actual measurement models. Figure 7 shows the |Z| curve of a 47uF tantalum capacitor. It reflects the impedance value of the capacitor at different frequencies (without considering phase information). As can be seen from the figure, the lowest impedance point of the capacitor is at 700K frequency, and the impedance is 8 milliohms.

Figure 7 Z curve of 47uF tantalum capacitor

This graph is a measured value and contains all information about the capacitor (except phase).

比如：它包含了电容的容量信息，一般容量越大的电容谐振点越低，要达到700k的谐振点，只有这种容值附近的电容才能够达到。0.1uf电容无论如何也达不到这个频点。它包含了ESL信息，假设ESL=0，则曲线是一条有斜率的直线。它也包含了ESR信息，比如谐振点处的8毫欧就是它的ESR值。所以，假如我们使用阻抗特性描述电容时，大家千万不要再使用蓄流的概念理解，比如，PMU上使用10uF电容和使用4.7uf电容从阻抗曲线上看有一些区别，但我们可以接受，此时千万不要再以蓄流为理由说10uF比4.7uF储能多，所以效果好，两种研究方法是从不同角度去分析同一个问题，交织在一起会混乱。建议使用阻抗法分析，可以做到定量分析。

举例说明，比如我们设计防浪涌电路，一般浪涌信号的波形如图8所示。

图8 0.5us-100kHz的浪涌波形

假设我们要消除图8所示的浪涌波形，需要加电容，但加多大的电容，如果从电容充放电角度去分析非常复杂，一两页纸张都不容易讲明白。

但假如从阻抗角度分析，我们只需要一个简单的要求，即加一颗电容，使得图8所示的谐波被短路到GND，浪涌就消除了。怎么实现这个要求呢，必须选择一颗电容，使得该电容对于该浪涌信号的频率下的阻抗最低即可。所以思路清晰了，按照两部走：

1 确定浪涌信号的频率。图8可以看出浪涌信号近似于正弦波，基波频率大概为100khz，只有在起始瞬间会有一些高次谐波，对于这个高次谐波可以估计一下，大概为几Mhz级别。

2 寻找两颗电容，一颗谐振点在100kHz的电容去消除浪涌信号中的基波信号。再找一颗谐振点在几Mhz的电容去消除浪涌信号中的高次谐波。假如对浪涌信号的高次谐波预估不确切，可以多加几颗其他可能的频段的电容。

实际操作中发现，即使470uf的电容，其谐振点也在200k，100khz的谐振点的电容估计更大。而手机根本不可能放置这么大的电容，所以只能看47uF（手机能放置的最大电容）对于100kz的阻抗了。470uF在200khz时阻抗为3毫欧，在100khz时为5毫欧姆。47uf在100khz时阻抗为40毫欧姆。可以接受，如果再并联一颗47uF电容，则100khz时阻抗减半，为20毫欧。个人认为对于浪涌信号，短路电阻为0.1欧姆以内就可以满足要求。根据这个要求，电容还可以变小一些。电容对于静电防护的原理也是一样的，防护之前必须知道静电的频谱。

对于图3那样的电容布局，实际上3颗47uF电容都对于浪涌有防护作用，但这三颗又不是直接的并联关系，下面详细分析这三颗电容对于静电防护的实际模型。

假如浪涌是从电池连接器处进入，则应该分析电池连接器处的阻抗。如图9所示，对于图3的布局电容进行了等效，等效之后可以看出，Zc1，Zc2布局位置较远，对于浪涌的防护不能使用电容测试模型，LX的加入，电容的|Z|曲线会向左边偏移，RX的加入，|Z|曲线会向上平移。移动的大小取决于LX，Rx的量值，这些都使得电容对于浪涌的防护能力变差。具体可以通过PCB仿真实现，通过仿真可以获知连接器入口处100khz的阻抗，从而知道对于浪涌防护的效果。一般来说，100k低频段，Lx的影响可以忽略。

图9 三颗不同位置的47uF电容对于浪涌的防护示意图

从上图可以看出，布局源的电容实际上也对浪涌的防护起到了作用，只是作用没有布局在连接器处得效果好，至于差别多少需要仿真去量化。

引申到我们工作中的例子，PA旁边放置22uF电容的作用是干什么的，2012解释为浪涌防护，而且还要求必须布置在pin脚附近，对于这个我不太理解，浪涌从哪里来？若从连接器处来，则应该优先布置在连接器附近。若从减小电压跌落角度考虑，我们来看看这个模型

从储能角度更好理解，PA需要电流时导致电压跌落，如果电容供给PA一部分电流，会小电压跌落，但是能减小多少呢，没办法量化。而从阻抗的角度分析，电源上出现了一个217Hz的方波，我们需要加电容将这个方波（可以认为是干扰波）短路到GND。方波的频谱包含了217Hz及其几次倍频，幅值最大的部分在基波，我们要首先想办法滤除基波，滤除的办法是找一颗谐振点在217Hz的电容，对于这么低的一个频率，我们可以认为ESL对其没有影响，那么电容容抗可以用理想模型1/jwc来计算，假设理想的阻抗为0.1欧姆，那么通过计算，需要的电容容量为7338uF。即使用标称6800,1000uf之类的电容滤波才能看到明显效果。那么我们22uF电容能有多大能耐呢！只能滤除一些倍频频谱。

从此例子可以看出，从储能角度能够解释的，使用阻抗也能解释，且使用阻抗分析方法可以很容易做到定量分析。

电源去耦涉及到很多问题：总的电容量多大才能满足要求？如何确定这个值？选择那些电 容值？放多少个电容？选什么材质的电容？电容如何安装到电路板上？电容放置距离有什 么要求？下面分别介绍。

目标阻抗（Target Impedance）定义为：

为要进行去耦的电源电压等级，常见的有5V、3.3V、1.8V、1.26V、1.2V 等。

为允许的电压波动，在电源噪声余量一节中我们已经阐述过了，典型值为2.5%。

为负载芯片的最大瞬态电流变化量。该定义可解释为：能满足负载最大瞬态电流供应，且电压变化不超过最大容许波动范围的情况下，电源系统自身阻抗的最大值。超过这一阻抗值，电源波动将超过容许范围。

对目标阻抗有两点需要说明：

1、目标阻抗是电源系统的瞬态阻抗，是对快速变化的电流表现出来的一种阻抗特性。

2 、目标阻抗和一定宽度的频段有关。在感兴趣的整个频率范围内，电源阻抗都不能超过这个值。阻抗是电阻、电感和电容共同作用的结果，因此必然与频率有关。感兴趣的整个频率范围有多大？这和负载对瞬态电流的要求有关。顾名思义，瞬态电流是指在极短时间内电源必须提供的电流。如果把这个电流看做信号的话，相当于一个阶跃信号，具有很宽的频谱，这一频谱范围就是我们感兴趣的频率范围。

需要多大的电容量：

有两种方法确定所需的电容量。第一种方法利用电源驱动的负载计算电容量。这种方法没有考虑ESL 及ESR 的影响，因此很不精确，但是对理解电容量的选择有好处。第二种方法就是利用目标阻抗（Target Impedance）来计算总电容量，这是业界通用的方法，得到了广泛验证。你可以先用这种方法来计算，然后做局部微调，能达到很好的效果，如何进行局部微调，是一个更高级的话题。下面分别介绍两种方法。

方法一：利用电源驱动的负载计算电容量

设负载（容性）为 30pF，要在 2ns 内从 0V 驱动到 3.3V，瞬态电流为：

如果共有36 个这样的负载需要驱动，则瞬态电流为：36*49.5mA=1.782A。假设容许电压波动为：3.3*2.5%=82.5 mV，所需电容量为

C=I*dt/dv=1.782A*2ns/0.0825V=43.2nF

Note: The added capacitor actually acts as an energy storage element to suppress voltage ripple. The capacitor must provide a current of 1.782A to the load within 2ns. At the same time, the voltage drop cannot exceed 82.5 mV, so the capacitance value should be calculated based on 82.5 mV. Remember: when the capacitor discharges and supplies current to the load, its voltage will also drop, but the amount of voltage drop cannot exceed 82.5mV (allowable voltage ripple). This calculation has no practical significance. The reason why I mention it here is to let everyone have a deeper understanding of the decoupling principle.

Method 2: Use target impedance to calculate capacitance

In order to clearly illustrate the calculation method of capacitance, we use an example. The decoupling power supply is 1.2V, the allowable voltage fluctuation is 2.5%, and the maximum transient current is 600mA.

Step 1: Calculate target impedance

Step 2: Determine the frequency response range of the regulated power supply.

It depends on the specific power supply chip used, usually between DC and several hundred kHz. Set here to DC to 100kHz. Below 100kHz, the power chip can respond well to transient current. Above 100kHz, it exhibits a very high impedance. If there is no external capacitor, the power supply fluctuation will exceed the allowed 2.5%. In order to still meet the voltage fluctuation requirement of less than 2.5% above 100kHz, how much capacitance should be added?

Step 3: Calculate bulk capacitance

When the frequency is below the self-resonance point of the capacitor, the impedance of the capacitor can be approximately expressed as:

The higher the frequency f, the smaller the impedance, the lower the frequency, the larger the impedance. In the frequency range of interest, the maximum impedance of the capacitor cannot exceed the target impedance, so the calculation uses 100kHz (the lowest frequency in the frequency range in which the capacitor acts, corresponding to the highest impedance of the capacitor).

Step 4: Calculate the highest effective frequency of the bulk capacitor

When the frequency is above the self-resonance point of the capacitor, the impedance of the capacitor can be approximately expressed as:

The higher the frequency f, the greater the impedance, but the impedance cannot exceed the target impedance. Assuming ESL is 5nH, the highest effective frequency is:

Such a large capacitor allows us to control the power supply impedance below the target impedance between 100kHz and 1.6MHz. When the frequency is higher than 1.6MHz, additional capacitors are needed to control the power system impedance.

Step 5: Calculate the capacitance required when the frequency is higher than 1.6MHz

If you want the power system to meet voltage fluctuation requirements below 500MHz, you must control the parasitic inductance of the capacitor. must be satisfied

Assuming that a 0402 package ceramic capacitor is used, the parasitic inductance is about 0.4nH.

The parasitic inductance of the via (the calculation method is provided later in this article) is assumed to be 0.6nH, then the total parasitic inductance is 1 nH. In order to meet the requirement that the total inductance is not greater than 0.16 nH, the number of capacitors we need in parallel is: 1/0.016=62.5, so 63 0402 capacitors are needed.

In order for the impedance to be smaller than the target impedance at 1.6MHz, the capacitance required is: