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Chengdu! Chengdu! - 2016 Cadence Product Technology Tour Exhibition

Latest update time:2016-04-29
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Theme 1 (Track 1): Simulation Design Session

Theme 2 (Track 2): High-speed PCB design and simulation sub-venue


Chengdu Station


Time: May 13 (Friday)

Location: Banquet Hall on the third floor of Sheraton Tianfu Lido Hotel, Chengdu
(No. 15, Section 1, Renmin Middle Road, Qingyang District, Chengdu, exit D from Luomashi Station of Metro Line 1, and walk 50 meters forward)


The 2016 Cadence Virtuoso Technology Seminar and Cadence Allegro and Sigrity Technology Tour Exhibition will be held in five cities including Xi'an, Chengdu, Shenzhen, Shanghai and Beijing in May. This conference will introduce you to Cadence's latest simulation technology progress. With the help of product demo demonstrations, user success case sharing and expert technical explanations, you can have a deeper understanding of how to better use Cadence technology. At the same time, at the one-day seminar, many R&D experts, product design service and technical support experts from Cadence headquarters and China will share with you Cadence's latest R&D results and progress in high-speed PCB design and simulation, and provide information to the electronics industry. Design engineers demonstrate Cadence's unique IC/Package/Broad co-design and system-level analysis solutions.


Please click "Read the original text" to register online, or reply your personal information directly to us in the following format, or send an email to: event_cn@cadence.com

Name – Chengdu, track 1 – Company – Email


For more information, please refer to:
http://www.cadence.com/cn/cadence/events/pcb_tot/pages/default.aspx


http://www.cadence.com/cn/cadence/events/Pages/EventDetails.aspx?eventid=186


Meeting agenda:


Track 1: Analog and Custom IC

Track 2: PCB design and Packaging

Registration

Registration

Virtuoso platform Overview

Allegro Keynotes

Introduction to the New Virtuoso® ADE Product Suite

Sigrity's Plans on Integrated Design and Simulation

Concurrent Design


Tea Break

Tea Break

Bridging Between Analog and Digital to Expedite Verification

What's new in Allegro Front End and Back End

Easily Add and Analyze Circuit Device Checks to Debug Problems

Advanced Wafer Level Packaging: Technology, Design Challenges, and Solutions

Buffet Lunch

Buffet Lunch

AMS-XPS-MS Verifying Complex Mixed-Signal SoCs

What's new in Sigrity 2016

Accelerating Custom/Analog Layout Productivity

Voltus+SPA: Sigrity Integrated IC-Package Co-analysis for Faster, IR-Drop Convergence Sign-off

Automating Analog/Mixed-Signal Chip-Level Routing VFP+VSR


Tea Break

Tea Break

Virtuoso Layout Electrically Aware Design

Power Integrity Design Automation

Circuit characterization

System Level Signal Integrity Sign-off Solution for Serdes and DDR Buses

Customer design experience sharing

Cross Fabric Design Environment

Lucky Draw & Wrap-up

Lucky Draw & Wrap-up



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