Cadence online seminar on December 14: Accelerating memory design, verification and parameter characterization to promote faster time to market

As the design develops towards higher-end process nodes, the design becomes more complex, and there are more PVT process errors to cover, which will also add extra time to the already tight design cycle. Designers are seeking to increase productivity while also seeking to reduce design, verification, and parameter characterization time to meet tight schedules, but current approaches are hampered by multiple tool and process challenges. implementation. The latest Cadence® Legato™ memory solutions are a one-stop shopping experience for all memory cell design, array and compiler verification and parametric characterization needs. Designers can use Legato memory solutions to achieve design closure quickly, thereby meeting users' time-to-market expectations.

In this workshop, designers will learn to:
• Maximize simulation throughput while maintaining high accuracy with the latest Super Sweep technology
• Maintain high accuracy during design, verification, and parameter characterization data consistency

Han Xiao - Product Manager of Cadence Company

Han Xiao has more than 20 years of rich experience in the EDA industry, and has successfully occupied a leading position in the market with a number of products. In the process of extensive cooperation with cutting-edge users, she was responsible for the development of multiple products from start to finish. She holds a bachelor's degree in electrical engineering from Ivy League Cornell University and an MBA from Boston University.

All users who participate in the seminar and complete the questionnaire will have the opportunity to receive Epson Runsense fitness smart watches (2 in total) provided by Cadence .
(The prizes are subject to actual objects, and the final right of interpretation belongs to Cadence. To ensure that you can receive the winning information, please update your personal information in time!)

Cadence is the world's leading provider of electronic design automation (EDA) and semiconductor intellectual property (IP). Our custom and simulation tools enable engineers to design the core components of system-on-chips (SoCs), including transistors, standard logic cells and IP blocks; our digital tools enable the design of gigabit and gigahertz SoCs using the latest semiconductor process nodes. Automated design and verification; our IC packaging and PCB tools enable complete circuit board and subsystem design.

Cadence also offers a growing portfolio of design IP and verification IP for memory, interface protocols, analog/mixed-signal components and specialized processors. In order to meet system-level design needs, Cadence also provides a complete set of software/hardware collaborative development platforms. Simply put, Cadence® technology helps customers design better products that connect the world.

For more details, please visit: www.cadence.com/cn

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