Cadence releases the industry's first new version of the digital full process based on machine learning engine
Cadence’s new version of digital process is fully optimized
Improve design quality and increase throughput by 3x
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Using a unified wiring and physical optimization engine, it has completed hundreds of successful wafer launches from 16nm to 5nm and smaller process nodes.
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The industry's first unified physical optimization engine that supports machine learning, with PPA improved by 20% compared to the previous generation process.
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The only digital full flow with integrated timing and voltage drop signoff engines, providing users with unique signoff closure
For more information please contact:
Cadence Newsroom
newsroom@cadence.com
Shanghai, China, March 18, 2020 - Cadence Electronics (Cadence, Inc., NASDAQ: CDNS) today released a new version of the Cadence digital full process that has been successfully tape-out verified hundreds of times on advanced process nodes, further optimizing power consumption and performance. and area, widely used in various fields such as automotive, mobile, networking, high-performance computing and artificial intelligence (AI). The process adopts a number of industry-first technologies such as unified placement and routing and physical optimization engines that support machine learning (ML) functions. The throughput is increased by up to 3 times and the PPA is increased by up to 20%, helping to achieve excellent design.
For more information about Cadence’s new digital process, please visit www.cadence.com/go/digital.
Through a number of key technologies, the new Cadence digital process has further improved PPA and throughput:
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Cadence digital full-flow iSpatial technology: iSpatial technology integrates the GigaPlace™ routing engine and GigaOpt™ optimizer of the Innovus™ design implementation system into the Genus™ comprehensive solution, supporting features such as routing layer distribution, effective clock skew and through-hole pillars. iSpatial technology allows users to use a unified user interface and database to complete the seamless transition from Genus physics synthesis to Innovus design implementation.
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Machine learning (ML) function: The ML function allows users to train iSpatial optimization technology with existing designs to minimize the design margin of the traditional placement and routing process.
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Optimized signoff convergence: The entire digital process adopts a unified design implementation, timing signoff and voltage drop signoff engine, which enhances signoff performance through the simultaneous convergence of all physical, timing and reliability target designs, helping customers reduce design margins. Reduce iterations.
"Based on the widely adopted integration process, the new enhanced digital full flow further strengthens Cadence's leadership in digital and signoff design and helps customers achieve SoC design excellence," said Cadence senior vice president and digital and signoff business Dr. Teng Jinqing, general manager of the department, said. "We work closely with our customers to alleviate the increasingly tight time pressure under large-scale design and provide all the necessary resources to efficiently achieve PPA goals."
▲Dr. Chin-Chi Teng, senior vice president and general manager of the Digital and Signoff Division at Cadence
The entire Cadence digital process includes Innovus design implementation system, Genus comprehensive solution, Tempus timing signoff solution and Voltus IC power integrity solution. The process provides customers with a faster path to design closure and greater predictability, supporting the company's Intelligent System Design™ strategy to enable design excellence for systems on a chip (SoC) at advanced process nodes.
client feedback
"We have been sparing no effort to enable high-performance cores to meet increasingly higher performance targets. Through the new ML capabilities of the Innovus design implementation system GigaOpt optimizer tool, we can quickly complete automatic training of the CPU core, increase the maximum frequency, and improve the timing Total negative margin is reduced by 80%. Total turnaround time for signoff design closure can be reduced by 2x.
-Dr. SA Hwang, General Manager of MediaTek’s Computing and Artificial Intelligence Technology Division
"Cadence digital full-flow iSpatial technology can accurately predict the optimization range of PPA for complete layout, achieve rapid iteration of RTL, design constraints and layout and routing, reduce total power consumption by 6%, and speed up design turnaround time by 3 times. At the same time, Cadence is unique The ML capabilities allowed us to train the design model on Samsung Foundry’s 4nm EUV node, achieving 5% additional performance improvement and 5% leakage power reduction.”
- Jaehong Park, Executive Vice President, OEM Design Platform Development, Samsung Electronics
About Cadence
With more than 30 years of expertise in computing software, Cadence is a key leader in the electronic design industry. Based on the company's intelligent system design strategy, Cadence is committed to providing software, hardware and IP products to help electronic design concepts become reality. Cadence's customers are the most innovative companies around the world, delivering products from chips, circuit boards to systems to the most dynamic application markets such as consumer electronics, hyperscale computing, 5G communications, automotive, aerospace, industrial and medical. Excellent electronic products. Cadence has been ranked among Fortune magazine's 100 Best Companies to Work For for six consecutive years. For more information, please visit the company's website at www.cadence.com.
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