Cadence and Samsung Foundry collaborate to accelerate ultra-large-scale computing SoC design at 4nm and beyond
Executive summary
● The entire digital process of Cadence 20.1 is fully optimized for Samsung Foundry’s advanced process nodes to achieve better PPA goals and help customers achieve a successful tapeout the first time.
● HPC reference design flow based on iSpatial technology facilitates rapid design implementation
● Cadence digital full-process machine learning and large/standard cell synchronization layout functions can help customers improve productivity and optimize designs
Shanghai, China, April 15, 2021 - Cadence Electronics (Cadence, Inc., NASDAQ: CDNS) today announced that it has launched the optimized Cadence® digital full flow version 20.1 for Samsung Foundry 4nm and higher process nodes . Based on this collaboration, designers can use Cadence tools to achieve better power, performance, and area (PPA) targets, as well as deliver accurate and first-time tape-out chips for ultra-large-scale computing applications.
Cadence Digital Process Version 20.1 provides customized optimization capabilities for Samsung Foundry's advanced process technology. For example, iSpatial technology can support seamless integration from Genus ™ Synthesis Solution to Innovus ™ Implementation System using a unified user interface and database.
Machine learning (ML) capabilities help users use existing designs to train GigaOpt ™ optimization technology to minimize design margins compared to traditional layout processes.
Combined with a high-performance clock network architecture, digital GigaPlace XL technology supports synchronous layout of large/standard cells and supports automated layout planning, thereby achieving higher design productivity while significantly optimizing line length and power consumption. The unified design implementation, timing and IR signoff engine further enhances signoff closure and reduces design margins and iteration times.
In order to accelerate the design process of Samsung Foundry's advanced process technology, a process for general high-performance computing (HPC) tasks such as large/standard cell synchronization layout, clock network, balanced H-shaped clock tree distribution, power output network and IR optimization has been launched. Example.
The complete Cadence RTL-to-GDS process is also optimized for Samsung Foundry's process technology, including Genus Synthesis Solution, Cadence Modus DFT software solution, Innovus Implementation System design implementation system, Quantus ™ Extraction Solution, Tempus ™ Timing Signoff Solution timing signoff solution, Tempus ECO Option, Tempus Power Integrity Solution power integrity solution, Voltus ™ IC Power Integrity Solution power integrity solution, Conformal ® Equivalence Checker equivalence checker, Conformal Low Power Low power tools, Litho Physical Analyzer, and CMP Predictor prediction tools.
Cadence 20.1 digital full process supports the company's Intelligent System Design ™ strategy (Intelligent System Design ™ ), helping customers achieve excellent SoC design. To learn more about Advanced Nodes digital design solutions, visit www.cadence.com/go/advnodes
About Cadence
With more than 30 years of expertise in computing software, Cadence is a key leader in the electronic design industry. Based on the company's intelligent system design strategy, Cadence is committed to providing software, hardware and IP products to help electronic design concepts become reality. Cadence's customers are the most innovative companies around the world, delivering everything from chips and circuit boards to the most dynamic application markets such as consumer electronics, hyperscale computing, 5G communications, automotive, mobile, aerospace, industrial and medical. Systematic excellence in electronics. Cadence has been ranked among Fortune magazine's 100 Best Companies to Work For for seven consecutive years. For more information, please visit the company's website at cadence.com.
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