New sinc filter structure optimized for synchronization.

By properly aligning the sinc filter’s impulse response to the PWM, alias-free ∑-∆ measurements can be achieved. Although this approach is simple, it is difficult (and in many cases impossible) to find an ideal system configuration. To illustrate this, assume that the sinc filter and PWM module share the same system clock source running at fsys _. The modulator clock, fmclk, _is then determined by Equation 1.

Where D _mclk is the clock divider of the modulator clock. Similarly, the PWM frequency f _pwm is determined by Equation 2.

where D _PWM is the clock divider that determines the PWM frequency. Finally, the decimation rate (data rate) of the sinc filter is determined by Equation 3.

Where D _dec is the clock division factor of the decimated clock. To avoid drift between impulse response and PWM cycles, the number of decimation cycles contained in one PWM cycle must be an integer:

Where N is an integer. Combining Formula 2, Formula 3 and Formula 4, we can get:

Clearly, there are only a limited number of choices for clock scaling, D _x, that satisfy Equation 5. Furthermore, the choice of clock scaling is often strictly limited. For example, a system may need to run at a certain PWM frequency (e.g., 10kHz) or use a certain modulator clock (e.g., 20MHz). Another complication is that there are limited choices for modulator clock selection. For example, if f _sys is 100 MHz, then the only reasonable choices for D _mclk are integers in a limited range between 5 and 10 (from 20MHz down to 10MHz).

Given all these constraints, it is difficult, if not impossible, to find a clock scaling that achieves the desired alignment between the impulse response and the PWM. What usually happens is that the user is forced to choose a clock scaling that satisfies Equation 5, rather than a clock scaling that produces the desired PWM frequency, modulator clock, and signal-to-noise ratio (SNR). Furthermore, if one of the frequencies varies over time, it is impossible to find a valid configuration. This situation is very common in multi-axis systems where a single motion controller synchronizes multiple motor controllers in a network.

While the alignment scheme provides excellent measurement performance, it has proven to be impractical. The following sections introduce a new sinc filter. This filter provides excellent measurement performance while allowing the user to select all clock dividers independently.

A traditional third-order sinc filter is shown in Figure 1. The filter generates the modulator clock for the ADC by scaling the system clock, and the ADC returns a 1-bit data stream to the filter. The filter function itself consists of three cascaded integrators 1/(1– z ^–1 ) (clocked at the same rate as the modulator) and three cascaded differentiators 1– z ^–1 (clocked at the decimation clock).

Figure 1. Traditional third-order sinc filter.

The sinc filter and ADC operate continuously with the same clock applied to them. Therefore, the filter continuously outputs data at a fixed rate determined by the decimated clock. The data rate from the filter is usually higher than the update rate of the motor control algorithm, so many of the filter outputs are rejected. Only when the impulse response is centered around the ideal measured value is the output captured and used as feedback.

With space vector modulation, the phase current average is taken only twice per PWM period. As a result, only two alias-free sinc data outputs are possible per PWM period, so there is no need to have the filter running continuously. It is actually sufficient to enable the measurement only when feedback is needed and disable it at all other times. In other words, the measurement runs in switching mode, unlike a traditional ADC.

The problem with switch-mode operation is that the modulator and filter clocks are derived from the same system clock. This means that both the filter and the ADC are running in switch-mode, which is not recommended as it will result in degraded performance. The reason for this is that the modulator in the ADC is a high-order system with some settling time and damping. Therefore, when the clock is first applied to the ADC, the modulator needs to settle before its output bit stream can be trusted. To address these issues, a new filter structure is proposed (see Figure 2).

Figure 2. The sinc filter is designed to operate in switching mode and refresh all states.

As a standard sinc filter, its core consists of three cascaded integrators and three cascaded differentiators. However, this filter has some features that allow new modes of operation. First, the filter has a new clock generator function that separates the modulator clock from the integrator clock. This allows the ADC to be clocked continuously, but the integrator clock is only enabled when a measurement is acquired. Second, the filter has a new filter control function. With the synchronization pulse as the reference, the control block handles all the timing and triggering required for the filter to operate. The main function of the filter controller is to refresh the filter, including initializing all filter states, timer filtering before starting a new measurement, and enabling/disabling the integrator clock when appropriate.

Finally, the filter has a new buffer and interrupt control unit that sorts all the output data and captures the correct measurement values. The buffer and interrupt unit also notifies the motor control application via an interrupt when a new measurement value is ready. The timing diagram in Figure 3 shows how this filter works.

Figure 3. Timing diagram of a sinc filter in switch mode.

To start the measurement, a synchronization pulse (sync pulse) is applied to the filter controller. Typically, this pulse indicates the start of a new PWM cycle. The sync pulse starts a timer that is configured to expire exactly 1.5 decimation cycles before the desired measurement point. The integrator clock and decimation clock are enabled at this point and the filtering process begins. After three decimation cycles (the settling time of a third-order sinc filter), the buffer and interrupt controller captures the data output and asserts the interrupt. Note how the measurement is centered around the sync pulse in Figure 3. The sequence repeats at the next sync pulse, but the modulator clock remains on after the filter begins operation.

The sinc filter described above solves the synchronization issues of conventional sinc filters. The filter and its operating modes do not make any assumptions about the PWM frequency, modulator clock, or decimation rate. It works equally well with all system configurations, even if the PWM frequency varies over time. Since the filter is effectively reset for each measurement, it is also insensitive to drift between clocks.

The authors have found that some publicly available sinc filter HDL examples have some shortcomings that can negatively affect the performance of the filter or cause unexpected behavior. This section discusses some implementation issues and how to design the HDL code to get the best performance on an FPGA.

The purest sinc3 filter consists of three cascaded integrators and three cascaded differentiators (see Figure 1). First, consider a pure integrator in z-domain ^{2 :}

Where u is the input and y is the output. The difference equation for the integrator is:

This first-order equation is equivalent to an accumulator, which is very suitable for implementation in clocked logic such as FPGAs. A common implementation method is a D-type flip-flop accumulator, as shown in Figure 4.

Figure 4. Accumulator implementation using D-type flip-flops.

This circuit can be implemented on an FPGA with only a few logic gates. Thus, when three pure integrators are cascaded, the transfer function in the z-domain is determined by Equation 8.

Equation 9 shows the difference equation for this three-stage cascaded integrator:

Note how the input for sample n affects the output for sample n.

If the D-type flip-flop accumulator shown in FIG. 4 is used to implement the third-order integrator, the result is shown in FIG. 5 .

Figure 5. A three-stage cascade accumulator implemented using D-type flip-flops.

Since this is a clocked circuit, it takes several clock cycles for a change in the input to affect the output. This becomes clearer when looking at the difference equation for the cascaded accumulator (see Equation 10).

This difference equation is completely different from the difference equation for a pure integrator (see Equation 9). For the accumulator, it takes two clock cycles for the input to affect the output, whereas for the pure integrator, the input affects the output immediately. To illustrate this, Figure 6 shows the step response of Equation 9 and Equation 10, respectively, for a unit step applied at sample number 5. As expected, the accumulator is delayed by two samples compared to the integrator.

Figure 6. Step response of three-stage cascaded integrators and three-stage cascaded accumulators.

Most publicly available sinc filter examples suggest using D-type flip-flop accumulators to implement the integrator. The primary reason for this is the low gate count required, but this simplicity comes at a price. The additional delay of two modulator clocks may seem insignificant compared to the group delay of the filter, but this delay affects the filter’s ability to attenuate high frequencies, so the accumulator implementation provides fewer effective bits than a pure integrator. Additionally, the flushing sinc filter described above requires an ideal transfer function to work properly. For these reasons, any sinc filter implementation should not rely on an accumulator to implement the integrator stage.

To obtain the ideal sinc3 response, it is recommended to implement the differential directly according to Equation 9. The result is shown in Figure 7. Note that the functional block diagram has two components: a clocked logic section (flip-flops) and a combinatorial section (summing). This implementation requires more gates, but it can provide the desired filter performance and delay.

Figure 7. Implementation of a three-stage cascaded integrator.

Similar to the integrator, many publicly available sinc filter examples implement the differentiator stage in an incorrect manner, resulting in degraded filter performance and unexpected delays. This section discusses the differentiator stage and provides recommendations on how to achieve the best performance with an FPGA implementation. First, consider the pure differentiator in the z-domain in Equation 11 and the corresponding difference in Equation 12.

To implement a differentiator on an FPGA, the most common approach is to use a D-type flip-flop (see Figure 8).

Figure 8. A differentiator implemented using a D-type flip-flop.

The following HDL code snippet illustrates a common approach to implementing a three-stage D-type flip-flop differentiator. Verilog pseudocode is used here, but the principles apply to other languages ​​as well.

Figure 9. A third-order differentiator implemented as clocked logic.

As with any clocked assignment, all statements on the right are evaluated first and assigned to the statements on the left. All statements are clocked and all assignments are updated in parallel. This creates a problem because the output term (y _x [n]) depends on the delayed terms (u[n-1] and y _x [n-1]), which need to be updated first. Therefore, the logical implementation of the above Verilog code snippet is shown in Figure 10.

Figure 10. Differentiator implemented by clock assignment.

Due to the clock assignment, the delay of the differentiator is 6 clock cycles instead of the expected 3 clock cycles. Since the differentiator is clocked by the decimated clock, the group delay and settling time of the filter are effectively doubled. However, this also affects the attenuation of the filter, and the frequency response is not an ideal third-order sinc. The implementation shown in Figure 10 is often seen in published sinc filter examples, but we strongly recommend choosing a method that emulates an ideal differentiator stage.

The above Verilog code snippet can be divided into two parts: the combinatorial part that calculates the current output and the clock logic part that updates the delay state. This separation allows the combinatorial part to be moved outside the functional block that is always controlled by the clock, as shown in the code snippet in Figure 11.

Figure 11. A third-order differentiator implemented using a mix of clocked logic and combinational logic.

When using combinatorial assignment, there is no additional delay associated with the yx calculation, and the total latency is reduced from 6 clock cycles to the ideal 3 clock cycles. The functional block diagram of the proposed differentiator implementation is shown in Figure 12.

Figure 12. A three-stage cascaded differentiator implemented using a mix of clocked logic and combinational logic.

Combining the above cascaded integrator and differentiator implementations allows the sinc filter to have ideal characteristics in terms of attenuation and delay. All ∑-∆ based measurements will benefit from this optimized filter implementation, especially the refreshing sinc which requires knowing the exact delay of the filter.

The proposed ∑-∆ measurement system has been implemented and tested in conjunction with a servo motor controller based on the Xilinx ^® Zynq ^® -7020SoCC. The system consists of a 60V 3-phase permanent magnet servo motor (Kinco SMH40S) and a 3-phase switched voltage source inverter. The SoC runs the field-oriented motor control algorithm and software to capture the measurement data in real time.

For phase current measurement, the system uses two isolated ∑-∆ ADCs (ADuM7701) followed by two third-order sinc filters. The sinc filter implementation uses the design recommendations discussed in this article, including the flushing sinc mode of operation. For comparison, two measurement results are shown for a traditional continuous mode filter and a flushing filter.

Although the control system has closed-loop field-oriented control, all measurements are made with open-loop control. Closed current loops are sensitive to measurement noise, and noise can couple through the current loop. By working in open loop, any effects from the current controller are eliminated, allowing a direct comparison of the results.

Except for the mode configuration and PWM alignment, the measurements were taken with the same configuration, including the decimation rate set to 125. Therefore, any difference in the measurement results will be a factor in whether the sinc3 pulse response can be properly aligned with the PWM. The control algorithm is executed at 10kHz and the modulator clock is 12.5MHz.

In the first example (see Figure 13a), the impulse response is uncorrelated with the PWM waveform. Figure 13b shows the measurement of two phase currents when the motor is stopped but the power inverter is switching at 50% duty cycle on all phases. The measurements in this operating mode show the noise level of the measurements. Figure 13b shows the phase currents when the motor is running open loop at 600rpm. The motor has four pole pairs, so the electrical period is 25ms. Both plots show significant noise, which will seriously affect the performance of any closed loop current controller. The noise level is independent of the amplitude of the fundamental phase current, so the noise performance is relatively worse at light loads. In this example, the noise is caused by the sinc filter impulse response being misaligned, so there is little or no increase in the decimation rate (attenuation) of the sinc filter.

Figure 13. Continuous mode operation with sinc filter impulse response not aligned with PWM.

Figure 14 shows the measurement results when the number of decimation cycles in each PWM period is an integer and the impulse response is aligned with the ideal measurement points. The results in Figure 14 can be directly compared to the results in Figure 13.

Comparing Figure 13 and Figure 14, it can be seen that although the filters use the same decimation rate, the noise level has been greatly reduced. These examples illustrate the importance of system configuration and synchronization to fully utilize the performance of a ∑-∆ based signal chain.

Figure 14. Continuous mode operation with sinc filter pulse response aligned to PWM.

Although the results of the continuously operating mode sinc filter shown in Figure 14 are satisfactory, the challenge with this filter is still finding a configuration that can achieve synchronization. While it is possible to synchronize a continuously operating mode sinc filter with PWM, it is not usually practical. Using a flushing sinc filter can solve this problem.

Figure 15 shows the measurement results of a flushing sinc filter. This filter was configured to run for only 3 decimation cycles around the ideal measurement point. As expected, the performance is similar to the continuously operating mode filter in Figure 14.

For comparison purposes, the flushing filter uses the exact same configuration as the continuous mode filter. The difference is that the continuous mode filter must use this configuration or performance will degrade, as shown in the results in Figure 13. In contrast, the flushing filter maintains optimal performance regardless of the system configuration.

Figure 15. Sinc filter pulse response flushed sinc filter aligned with PWM.

The noise level of the unaligned continuous mode sinc filter (Figure 13a) is about 120 LSBs of a 16-bit signal. This is equivalent to the loss of the lower 7 bits of signal due to noise. The noise level of the flushing sinc filter (Figure 15a) is about 5 LSBs of a 16-bit signal, which is equivalent to the loss of less than 3 bits of signal due to noise.