ADI In-depth丨Example Analysis of Phase Calibration and Control of PLL Devices!

Until recently, little attention has been paid to the phase behavior in these circuits. However, as the demands for efficiency, bandwidth, and performance grow, RF engineers must come up with new techniques to improve spectral and power efficiency. Repeatability, predictability, and adjustability of signal phase all play an increasingly important role in modern communications and instrumentation applications.

Phase measurements are meaningless if not relative to another signal or to the original phase. For example, phase measurements on a two-port network such as an amplifier using a vector network analyzer (VNA) measure the output phase relative to the input phase ANG (S21). A single input phase is the reflected phase relative to the incident phase ANG (S11). On a PLL synthesizer, phase measurements are relative to an input reference phase or between signals. The ideal state of any phase measurement is to measure the exact expected value compared to the original phase, but nonlinearities, nonidealities, temperature differences, board traces, and other manufacturing variations can make phase more susceptible to variation in signal generation. For this article, "in phase" refers to signals with identical amplitude and timing characteristics; deterministic phase refers to signals with known and predictable phase shifts between them.

To compare the phase of two different frequencies, a high-speed oscilloscope can be used to compare the output phase to the reference phase, which is a relatively intuitive method. In order to be intuitive, the input phase and output phase must usually be integer multiples of each other. This is relatively common in many clock circuits. For integer-N PLLs, the relationship between the input frequency (REF _IN ) and the output frequency (RF _OUT ) is usually determined and repeatable. Simply place the oscilloscope probes on REF _IN and RF _OUT , but be careful to only capture the signal when the phase is determined to have been established. Advanced oscilloscopes like the RTO1044 allow event triggers to activate only when certain conditions are met: such as when a specific digital pattern is written to the PLL device and when the rising edge of a known signal occurs. Given that there may be some delay between the writing of the digital pattern and the final signal stabilization, it is critical to insert some delay between these two events, and this particular model of instrument can achieve this function.

The measurement in Figure 1 is to confirm that the phase delay of the ADF4356 PLL relative to a known reference signal (in this case, another ADF4356 set to the same output frequency) is constant and repeatable at power-up. To properly set up the instrument, two low speed probes are connected to the CLK and DATA lines of the ADF4356 SPI interface. To write a digital pattern to a specific frequency, you must wait 1 second before the instrument can capture a time domain plot showing the outputs of the two PLLs.

Figure 1. Integer-N setup.

For this measurement, two ADF4356 PLLs were locked to a VCO frequency of 4 GHz and divided down from 8 MHz to 500 MHz, with one PLL repeatedly powered on and off using the software power-down feature. The oscilloscope was used in infinite persistence mode to take 119 acquisitions, and the phase difference between the two PLLs was constant and repeatable. To ensure that the phase difference is repeatable, a number of considerations must be followed. Low R divider values ​​introduce less uncertainty than high R divider values, and it is critical to feed the divided feedback from the VCO output to the N counter input. Given that the ADF4356 PLL and VCO contain 1024 different VCO bands, it is important to use a manual calibration override procedure to eliminate this uncertainty.

Phase resynchronization is the ability of a fractional-N PLL to return to the same phase shift at each given frequency. That is, frequency A with phase P1 is changed to frequency B and when the frequency is reset back to F1, the same original phase P1 is observed. This definition ignores changes caused by VCO drift, leakage current, temperature changes, etc.

Resynchronization sends a reset pulse to the fractional-N sigma-delta modulator, putting it in a known, repeatable state. This reset pulse needs to be applied after the frequency settling mechanisms such as VCO band selection and loop filter settling time have completed. Its value is controlled by the timeout counter in Register 12. Recent PLLs have the ability to adjust the timing of this reset pulse, allowing a degree of output signal adjustability. In addition, it is possible to change the timing in 360°/2 ²⁵ steps, making measurements easier than with most instruments.

Figure 2. Fractional-N resynchronization with a frequency range of 4694 MHz to 4002.5 MHz.

For this experiment, both ADF4356 VCOs were set to 4002.5 MHz divided by 8. The second PLL’s VCO frequency was set to 4694 MHz and then set back to 4002.5 MHz. Examining the PLL behavior with an oscilloscope showed that after 1700 frequency changes, the PLL settled to the same phase each time.

To characterize the different phase shift characteristics, the phase word is set to 4194304/2 ²⁵ (equivalent to 90°). Similar values ​​are set for 90°, 180°, 270°, and 0°, and the oscilloscope is viewed again (Figure 3).

Figure 3. Phase resynchronization with variable phase shift.

Four equally spaced signals are observed relative to the original signal on channel 1, confirming the accuracy of the phase resynchronization with programmable offset.

This feature is very useful and means that a lookup table of phase values ​​can be created for each user frequency, recording the phase value each time it is used. In applications where four in-phase LO frequencies need to be combined, the phase resynchronization and offset functions are used to adjust the output phase to collectively provide 6dB lower phase noise. If used as an adjustable LO (perhaps on the first stage of a signal analyzer), the resynchronization and phase shift functions allow the user to perform a one-time calibration at power-up to determine the exact phase value of each LO. When used as a LO, the phase value can be set per LO as required, eliminating the need to perform a calibration at each frequency.

Figure 4. Phase-critical applications that require precise control of the PLL output phase.

For phase-critical applications like network analyzers, the circuit can measure the phase value at each frequency at power-up and then set it as needed because the LO operates over the entire range of interest.

Vector signal and network analyzers can also be used to characterize phase behavior, although their use is limited to comparing the phase of the device to its initial value. Advanced analyzers such as the FSWP can be placed in FM demodulation mode and the phase output selected.

This is very useful for evaluating the phase resynchronization feature on the ADF4356 PLL. The trace below (Figure 5) shows that the ADF4356 phase changes by 180° at an output frequency of 5025MHz.

Figure 5. FSUP FM demodulator output with 180° phase shift.

The phase adjustment function avoids resetting the sigma-delta modulator by simply adding a phase word between 0° and 360° to the existing phase. This is useful in applications where phase resetting is undesirable. It can be used to dynamically adjust the phase word to compensate for phase differences due to effects such as temperature.

Phase adjustment adds phase to the existing signal every time R0 is updated (with the programmed value of Register 3). It does not include reset pulses such as phase resynchronization. The following measurement results from FSWP show the original signal with 90° (Figure 6) and 270° (Figure 7) added. In both cases, the output frequency of the ADF4356 was set to 5025 MHz before the phase change.

Figure 6. 90° change

Figure 7. 270° change

As the physical parameters of an inductor change with temperature, so do its electrical characteristics, which manifest as a phase change. To reduce this phase change, the user can set the desired phase shift to maintain the same phase. Two ADF4356 PLLs set to 4GHz output frequency, placed in the same oven chamber with the same phase, closely tracked each other’s phase (Figure 2), demonstrating that the user can adjust the phase based on temperature.

Figure 8. Phase drift of the ADF4356 over temperature, measured at a VCO frequency of 4 GHz.

Beamforming is a key technology that enables 5G network architectures. These networks use multiple antenna array elements, each with different phase and amplitude, to direct antenna energy directly to the end user. For this application, phase repeatability is key. Beamforming requires repeatability of the LO phase, and if there is uncertainty in this phase, additional calibration of the beamforming circuit is required.

Figure 9 shows the directivity of two half-wave elements separated by a quarter wavelength and driven in phase. The antenna radiation pattern is nearly omnidirectional, with no beamforming observed. Figure 10 shows two elements driven by a 90° out-of-phase signal, and the resulting radiation pattern shows a more focused radiation pattern. As the number of element arrays increases, the accuracy of the radiation pattern toward the end user also improves, further improving spectral efficiency.

Figure 9. No beamforming

Figure 10. Beamforming

The phase resynchronization feature ensures that the uncertainty in the LO phase characteristics is eliminated. In addition, the ability to adjust this phase provides the user with another method to overcome any additional phase delays that exist in the circuit that are difficult to adjust for in the beamformer or baseband circuits.

Phase resynchronization places the ADF4356 and similar PLL devices into a known phase, which enables many applications and greatly simplifies calibration procedures.