How can the performance of voltage regulators be improved in low voltage and high current applications?

The multiphase buck regulator uses the TLVR schematic from Figure 1. While the main inductor windings are still connected between phase and the switching node of VO _, the added auxiliary windings are electrically connected in series with each other and to the tuning inductor _LC . If L _C is removed , the circuit returns to having only the discrete (uncoupled) inductor in a buck converter. If the L _C output is short-circuited, the correlation between the phases is strongest and transient performance is fastest, but this will also affect the current waveform and the general amplitude of the current ripple. In fact, LC _is usually a compromise between these two extreme cases.

Figure 1. TLVR schematic diagram

As with any multiphase buck converter, when a fast transient load step arrives, changes in output voltage cause feedback to react, adjusting voltage and current accordingly. For TLVR, one potential problem is that all auxiliary windings are connected in series, and the transformer turns ratio to the main winding is typically 1:1. There is a square wave applied at the switching frequency on the TLVR main winding, and ideally there is a temporal phase shift between the different phases. But during transients, these phases often align to improve performance.

Consider an aggressive ground load transient in a 12V to 1.8V application, all high side FETs in all phases are on to allow the inductor current to rise as fast as possible, so (V _IN - V _O ) = 10.2V is applied simultaneously All main windings are shown in Figure 2. The actual waveform will depend on the circuit parameters, but in the worst case, a 1:1 transformer will generate 10.2V on its secondary side, so the voltage pulse on the secondary side will be (V _IN - _VO ) × N _PH . This is obviously a security concern. Figure 2 gives actual values ​​for a TLVR value of 150nH, with a small leakage inductance between the main and auxiliary windings measuring 5nH. The figure also shows an L _C value of 160nH. This L _S value is within the typical range of NPH _~ 6, but can be adjusted, especially for different numbers of associated phases.

Figure 2. Equivalent schematic for TLVR = 150nH, worst-case loading transient

Figure 3. TLVR worst-case transient simulation: a) L _C = 160nH, b) L _C open circuit, N _PH = 20

Figure 3 shows a simulation for N _PH = 20 with 100ns pulses at 10.2V for all VX switch nodes: LC _{= 160nH in Figure 3a and LC} = open circuit in Figure 3b . All secondary TLVR voltage curves are plotted to show how the series connection of the windings gradually increases the voltage. When L _C = 160nH and 20 secondary windings of associated phases are loaded, the voltage on the board reaches approximately 123V. But with L _C disconnected, the voltage step can be as high as 197V because there is no load on the secondary side. The total voltage is closer to the worst case (V _IN - _VO ) × N _PH .

However, the results in Figure 3 are still too optimistic. In fact, the simplified simulation in Figure 3 requires at least the addition of parasitic capacitance between the GND plane and the fairly wide trace connecting the secondary TLVR winding. A realistic estimate of these parasitic capacitances is around 5pF. As shown in Figure 4, add a 5pF capacitor to each TLVR secondary node to obtain the simulation shown in Figure 5. The added parasitic capacitance causes a lot of oscillation in high-Q circuits because the resistance is kept to a minimum for efficiency and transient considerations. The same NPH ₌ 20 case shows: when L _C = 160nH is present, the voltage peak is 239V; if L _C is disconnected from the board, the peak voltage is 390V.

Note that the value of the layout parasitic capacitance is not important - it only affects the frequency and envelope of the oscillations, but not the amplitude.

图4. 布局电容被添加到TLVR等效瞬态原理图中

至少有两种方法可减轻这种高压问题。一种是确保各相位在瞬态期间不对齐，或者对齐相位不超过2到3个。控制器设计可以考虑这种方法，但很显然，它会限制瞬态响应可达到的速度。另一种方法是限制TLVR关联相位的数量。但是，鉴于N _PH 需要足够高以便约束电流纹波，同时N _PH 也需要足够低以便限制最坏情况下的副边电压，因此这种方法的实际限值是多少？

图5. TLVR最坏情况瞬态仿真，每个副边节点添加5pF电容：a) L _C = 160nH，b) L _C 开路，N _PH = 20

TLVR中电流纹波的一个推导式如所示。它对任何占空比值都有效，但由于等效电路为该推导式进行了简化（各TLVR中没有专用漏电感L _K 作为一个单独元件），它对于L _C = 开路是准确的，但随后便开始累积误差，当L _C = 短路时误差达到无穷大。它还假设TLVR漏电感L _K <<L _M 。尽管如此，当L _C 不是太小且L _K 不是太大时，它仍能提供一个非常合理的估计值。图6比较了中耦合电感的归一化电流纹波和中作为V _O 函数的TLVR的电流纹波(V _IN = 12V)。换句话说，从分立电感L（红色曲线）开始，不同数量的N _PH ：a) 作为单个耦合电感发生磁耦合，或 b) 作为TLVR以电气方式关联。具体条件设置如下：TLVR = 150nH，漏电感为5nH，L _C = 120nH，假设耦合电感的耦合比L _M /L _K = 5。根据N _PH ，在相同L值下，磁耦合电感显著降低了来自分立电感的电流纹波。电流纹波曲线在D = V _O /V _IN = k/N _PH 处有陷波或局部最小值。将LM增加到无穷大会使这些地方的电流纹波等于零。另一方面，TLVR电流纹波总是比相同L值下分立电感的电流纹波大。TLVR电流纹波在D = K/N _PH 区域也有陷波，这些地方的电流纹波接近分立电感L的电流纹波。通过增加关联相位的数量，N _PH 显然对降低TLVR电流纹波有利（图6b）。

图6. 不同N _PH 的计算归一化电流纹波与V _O 的关系(V _IN = 12V)：a) 耦合电感(L _M /L _K = 5)，b) TLVR = 150nH (L _C = 120nH)

图7显示了TLVR = 150nH和不同L _C 值下作为关联TLVR相位的函数的电流纹波。L _C 值越低，引入的误差越大，但趋势非常清晰；降低N _PH 或降低L _C 会导致电流波纹增加。请注意，TLVR始终具有比基线分立电感（L _C = 开路）更大的纹波。假设L _C 值足够大，可以得出结论，为使电流纹波影响受控，关联相位的最小数量应在N _{PH_min} ~1/D左右，参见公式(1)。换句话说，N _PH 至少应提高到电流纹波曲线的第一陷波；在这里，不同相位的占空比接近重叠。

图7. 不同LC 下TLVR = 150nH的计算电流纹波与关联NPH的关系（V _IN = 12V，V _O = 1.8V，f _S = 400kHz）

另一个结论是，V _O 越低，则所需的最低关联相位数量越多，因为N _{PH_min} = V _IN /V _O 。对于V _IN = 12V且V _O = 1.8V，TLVR解决方案大约需要N _{PH_min} ~6，而对于V _O = 0.8V，大约需要N _{PH_min} ~15，参见图8。当然，如果对电流纹波有额外的影响，并且可以容忍效率的降低，那么更少数量的N _PH 也是可以接受的。请注意，为了一致性，图8是针对相同的TLVR = 150nH和相同的L _C 值绘制的，与V _O = 1.8V情况相同。这导致电流波纹较小。但是，降低的V _O 会使瞬态性能更差，因此TLVR解决方案很有可能会调整以改善瞬态，导致电流波纹增加。

假设在12V转1.8V应用中，关联N _PH = 6为目标的话可使TLVR电流纹波保持较低水平。图9显示了原边上所有相位都有100ns脉冲时的最坏情况下的副边TLVR电压(V _IN - V _O )。当存在L _C = 120nH时，副边电压可以达到77V。如果L _C 从PCB断开，则无负载的副边电压可以振荡幅度达到113V。

图8. 不同LC 下TLVR = 150nH的计算电流纹波与关联NPH的关系。V _IN = 12V，V _O = 0.8V，f _S = 400kHz

图9. TLVR最坏情况瞬态仿真，每个副边节点添加5pF电容：a) L _C = 120nH，b) L _C 开路，N _PH = 6

对最坏情况副边TLVR电压的粗略估计如式(2)所示，其中2x乘数来自振荡而不是脉冲波形。

TLVR内部泄漏使此电压峰值略微降低，但在设计保证下该泄漏一般较小。相应地，对于N _PH = 20，估算V _PEAK 为408V；对于N _PH = 6，估算电压峰值为122V，而仿真结果分别为377V（图5b）和113V（图8b）。

In order to make the secondary voltage lower than the expected minimum VPEAK in the worst case _, the estimated N _{PH_max} is roughly as shown in Equation (3). Assuming that the maximum rated value of the PCB is limited to 60V, N _{PH_max} < 2.9 for 12V to 1.8V applications; N _{PH_max} < 2.6 for 12V to 0.8V applications. This creates problems in constraining the current ripple, since N _{PH_min} = 6 for VO = 1.8V and _N PH_min ₌ 15 for _VO = 0.8V. If safety ratings require sufficiently low voltage limits, then in practical applications an increase in additional current ripple appears to occur, so a more significant efficiency impact is expected.

Figure 10 shows NPH_min ₍ efficiency) and NPH_max ₍ safety) versus VO _, assuming safety ratings of VPEAK ₌ 60V and _VIN = 12V. Possible solution between N _{PH_min} and N _{PH_max only exists above V O} = 3.5V, while at lower voltages N _{PH_MAX} overrides it due to safety issues, resulting in higher current ripple and related efficiency impact .

Figure 10. _{NPH_min} (efficiency) and NPH_max ₍ safety) versus VO _, assuming VIN ₌ 12V and safety rating VPEAK ₌ 60V

Of course, if N _PH is lowered , this will also result in an increase in the total number of external tuning inductors LC _, since one is required for each associated winding.

The TLVR method is an improvement over the discrete inductor solution, but it mainly improves the transient state and produces current ripple, thus worsening the efficiency. To keep the current ripple effects under control, it is recommended to relate N _{PH_min} > V _IN /V _O . From a safety perspective, if the worst-case voltage on the PCB is expected to be the VPEAK limit, then the number of associated phases needs to be no more than N _{PH_max} < V _PEAK /((V _IN - _VO ) × 2). Safety standards generally override current ripple considerations, so it is expected that the current ripple and efficiency of the TLVR method will be affected.

Another possibility to solve the high voltage problem is to ensure that the number of phases the controller is aligned with never exceeds the maximum number determined based on N _{PH_max} above (the 60V limit is 2 to 3 phases at most, etc.). The challenge with this approach is that it limits how quickly the system's transient performance can respond. Excessive phase overlap during steady-state operation should also be considered.