Next is the Q&A session - 11 common PLL chip interface problems

Waveform: It can be a sine wave or a square wave.

Power: Meet the reference input sensitivity requirements.

Stability: TCXO is usually used, and the stability requirement is < 2 ppm. Here are several reference stability indicators and phase noise indicators.

Frequency Range: PLL products provided by ADI can also operate at frequencies lower than the minimum reference input frequency, provided that the conversion rate of the input signal meets the given requirements.

All ADI PLL product control interfaces are three-wire serial control interfaces, as shown in Figure 1. It should be noted that in ADI's PLL products, most of the timing diagrams are shown in the upper figure in Figure 1, which is wrong. The correct timing diagram is shown in the lower figure in Figure 1. The rising edge of LE should be aligned with the rising edge of Clock, not the falling edge of Clock.

Figure 1. Serial control interface of PLL frequency synthesizer (3-wire serial interface)

The control interface consists of clock CLOCK, data DATA, and load enable LE. The falling edge of load enable LE provides synchronization for the start serial data. The serial data is first shifted into the shift register of the PLL frequency synthesizer, and then the corresponding internal register is updated at the rising edge of LE. Note that there are two LE control methods in the timing diagram.

The SPI control interface is 3V/3.3V CMOS level. In addition, it should be noted that when writing to the registers of the PLL chip, it is necessary to write in a certain order. Please refer to the description in the chip data for details. In particular, when operating the registers of the ADF4360, it is necessary to pay attention to the delay between writing the control register and the N counter.

The control signal can be generated by MCU, DSP, or FPGA. The generated clock and data must be clean and have small overshoot. When using FPGA to generate, competition and risk phenomena should be avoided to prevent glitches. If glitches cannot be avoided, a 10~47pF capacitor can be connected in parallel to the data line and clock line to absorb these glitches.

Generally, the signals that control PLL include: CE, LE, CLK, DATA. CLK and DATA signals can be shared, that is, they occupy two MCU IO ports, and the LE signal is used to control which PLL chip is operated. Multiple LE signals can also share an MCU IO port, in which case the CE signal is needed to control the power on and off of the chip.

ADIsimPLL V3.3 frees application engineers from complicated mathematical calculations. We only need to input several key parameters for setting the loop filter, and ADIsimPLL can automatically calculate the values ​​of the filter components we need. These parameters include phase detection frequency PFD, charge pump current Icp, loop bandwidth BW, phase margin, VCO control sensitivity Kv, filter form (active or passive, order). The calculated results are often not the values ​​of the components we can buy on the market, so just choose the one that is closest to the component.

The relationship between the filter open-loop gain and closed-loop gain and the phase noise graph. The corner frequency of the closed-loop gain is the loop bandwidth. On the phase noise graph, this point corresponds to the corner frequency of the phase noise curve. If the designed phase-locked loop noise is too large, the corner frequency seen on the spectrum analyzer will be greater than the set loop bandwidth.

Active filters introduce noise because of the use of amplifiers, so the phase noise performance of the frequency generated by the PLL using active filters will be worse than that of the PLL output using passive filters. Therefore, we try to use passive filters in the design. Among them, the third-order passive filter is the most commonly used structure. The charge pump voltage Vp of the PLL frequency synthesizer is generally 5V or slightly higher, and the maximum control voltage of the charge pump current after integration through the loop filter is lower than Vp or close to Vp.

If the control voltage of VCO/VCXO is within this range, the passive filter is fully capable; if the control voltage of VCO/VCXO exceeds Vp, or is very close to Vp, an active filter is required. While filtering the loop error signal, it also provides a certain gain, thereby adjusting the VCO/VCXO control voltage to the appropriate range.

So how do you choose an amplifier for an active filter? This type of application mainly focuses on the following technical indicators:

If the power supply is single, you need to consider using a rail-to-rail output amplifier.

When selecting a VCO, try to choose a control voltage that corresponds to the VCO's output frequency at the midpoint of the available tuning voltage range. Selecting a VCO with a low control voltage can simplify the PLL design.

The output of the VCO is distributed through a simple resistor distribution network. From the output of the VCO, the impedance of the resistor network is 18+(18+50)//(18+50)=52ohm. This matches the output impedance of the VCO. The power relationship of points ABC in the figure below. The power of points B and C is 6dB less than that of point A.

The following figure shows the output matching circuit of ADF4360-7 when the output frequency is 850MHz~950MHz. Note that this example matches to a 50 ohm load. If the load is 75 ohms, the matching circuit does not need to be changed. The output stage of ADF4360-7 is a current source, and a small change in the load value will not cause a big impact, but it should be noted that the loads at the differential output terminals must be equal.

In the following cases, the polarity of the charge pump is positive.

In the following cases, the polarity of the charge pump is negative.

There are two types of PLL lock indication: analog lock indication and digital lock indication.

Phase detector and charge pump schematic

Number lock indication:

When the phase error at the PFD input is detected to be less than 15ns for 3(5) consecutive times, the PLL will give a digital lock indication.

The operating frequency range of the digital lock indication is usually 5kHz~50MHz. At lower PFD frequencies, leakage current will trigger the lock indication circuit; at higher frequencies, the 15ns time margin is no longer suitable. Outside the operating frequency band of the digital lock indication, it is recommended to use the analog lock indication.

Simulate lock indication:

The pulse train is obtained by XOR processing the Up pulse and Down pulse at the charge pump input. Therefore, when locked, the output of the lock indication circuit is a high-level signal with a narrow negative pulse train. The figure shows a typical analog lock indication output (when a pull-up resistor is added to the MUXOUT output terminal alone).

The output stage of the analog lock indication is an N-channel open-drain structure, which requires an external pull-up resistor, usually 10KOhm~160kohm. We can get a flat high-level output through an integration circuit (low-pass filter), as shown in the blue box circuit.

A condition for false locking:

The reference signal REFIN signal is lost. When the REFIN signal is disconnected from the PLL synthesizer, the PLL will obviously lose lock; however, the ADF41xx series PLL uses the REFIN clock to check whether it is locked. If the PLL has been locked before, the REFIN clock is suddenly lost and the PLL will continue to show the locked state. The solution is to use the analog lock indication.

When VCXO replaces VCO, the PLL often loses lock. Take ADF4001 as an example. The input impedance of VCXO is usually small (relative to VCO), about 100kohm. In this way, the current required by VCXO must be provided by PLL. PFD=2MHz, Icp=1.25mA, Vtune=4V, VCXO input impedance=100kohm, VCXO control port current=4/100k=40uA. At the PFD input, the static phase error required to offset the input current of VCXO is

16ns>15ns, so the digital lock indication is low.

Solution 1 : Use a simulated lock indicator.

Solution 2 : Use higher charge pump current to reduce static phase error. Increase the loop filter capacitor to make the discharge slower.

Frequency specification: It can work at a frequency lower than the minimum RF input signal frequency, provided that the RF signal Slew Rate meets the requirements.

For example, the ADF4106 data sheet specifies a minimum RF input signal of 500MHz and a power of -10dBm, which corresponds to a peak-to-peak value of 200mV and a slew rate of 314V/us. If your input signal frequency is lower than 500MHz, but the power meets the requirements and the slew rate is greater than 314V/us, then the ADF4106 can also work properly. Usually, the conversion rate of the LVDS driver can easily reach 1000V/us.

The PLL power supply and the charge pump power supply are required to have good decoupling. In comparison, the charge pump power supply has more stringent requirements. The specific implementation is as follows:

Place capacitors of 0.1uF, 0.01uF, and 100pF at the power pins in turn. Filter out the interference on the power line to the maximum extent. The equivalent series resistance of large capacitors is often large, and the filtering effect on high-frequency noise is poor. The suppression of high-frequency noise requires capacitors with small capacitance. As can be seen in the figure below, as the frequency increases, after a certain turning frequency, the capacitor begins to show the characteristics of an inductor. Different capacitance values ​​often have different turning frequencies. The larger the capacitance, the lower the turning frequency, and the worse its ability to filter high-frequency signals.

In addition, connecting a small resistor (18ohm) in series with the power line is also a common method to isolate noise.

The center frequency of the VCO is determined by the following three factors.

1) VCO capacitor C VCO

2) Inductance L BW introduced by the bond wires inside the chip

3) External inductor L EXT .

The first two items are determined by the device, so as long as an external inductor is given, the output center frequency of the VCO can be obtained. The control sensitivity of the VCO is given in the corresponding data sheet. As an example, the figure below shows the integrated VCO characteristics of the ADF4360-7.

ADF4360-7 VCO output center frequency vs. external inductance

ADF4360-7 VCO sensitivity vs. external inductance

When selecting an inductor, it is best to choose one with a high Q value. Coilcraft is a good choice. Common inductors on the market are basically above 1nH. Smaller inductors can be made with PCB wires. Here is a simple formula for calculating the inductance of PCB leads, as shown in the figure below.

Model of wire inductance

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