CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319 CMOS Crystal
Clock Generators
September 1995
Revised March 1999
CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 •
CGS3316 • CGS3317 • CGS3318 • CGS3319
CMOS Crystal Clock Generators
General Description
The CGS3311, CGS3312, CGS3313, CGS3314,
CGS3315, CGS3316, CGS3317, CGS3318 and CGS3319
devices are designed for Clock Generation and Support
(CGS) applications up to 110 MHz. The CGS331x series of
devices are crystal controlled CMOS oscillators requiring a
minimum of external components. The 331x devices pro-
vide selectable output divide ratio (and selectable crystal
drive level). The circuit is designed to operate over a wide
frequency range using fundamental model or overtone
crystals.
Features
s
Fairchild’s CGS family of devices for high frequency
clock source applications
s
Crystal frequency operation range:
fundamental: 10 MHz to 100 MHz typical
3rd or 5th overtone: 10 MHz to 85 MHz
s
Programmable oscillator drive
s
Selectable fast output edge rates
s
Output symmetry circuit to adjust 50% duty cycle point
between CMOS and TTL levels
s
Output current drive of 48 mA for I
OL
/I
OH
s
FACT™ CMOS output levels
s
Output has high speed short circuit protection
s
Basic oscillator type: Pierce
s
Hysteresis inputs to improve noise margin
Ordering Code:
Order Number
CGS3311M
CGS3312M
CGS3313M
CGS3314M
CGS3315M
CGS3316M
CGS3317M
CGS3318M
CGS3319M
Package Number Package Description
M08A
M08A
M08A
M08A
M08A
M08A
M08A
M08A
M08A
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
FACT™ is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS010980.prf
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CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319
Connection Diagrams
(A) 3311
(E) 3315
(B)3312
(F) 3316
(C) 3313
(G) 3317
(D) 3314
(H) 3318
(I) 3319
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2
CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319
Truth Tables
Division Selection
DIVB DIVA OEL
F
1
0
F
1
0
X
X
0/F
0/F
0/F
1
1
1
X
X
X
0
0
0
0
0
1
X
OEH Divider Output
X
1
1
1
1
1
X
0
Divide-by 1
Divide-by 2
Divide-by 4
Divide-by 8
Divide-by 16
Divide-by 32
Output Reset HIGH
at Re-enable
Output Reset HIGH
at Re-enable
OSC_DR
0
1
F
Rise and Fall Time Selection
OSC_DR DIV TRF Rise/Fall Time (ns)
F
F
F
F
0,1
0,1
N
N
Y
Y
X
X
0/F
1
0/F
1
0/F
1
2
less than 2
4
2
4
2
Drive Selection
Drive
Low
Medium
High
Note:
Actual value of the floating OSC_DR and DIVB input is V
CC/2
Note:
Where “F” indicates floating the input.
Pin Descriptions
Note: Pin out varies for each device.
OSC_IN
Input to Oscillator Inverter. The output of the
crystal would be connected here.
OEL
Active LOW 3-STATE enable pin. This pin pulls
to a low value when left floating and 3-STATE
the output when forced HIGH. This pin has TTL
compatible input levels.
Rise and Fall time override pin. Available only
for die form.
This pin is the main clock output on the device.
The Oscillator LOW pin is the ground for the
Oscillator.
This pin is the same signal as OSCLO_1. It has
been provided as an alternate connection for
OSCLO_1 for hybrid assemblies.
The power pin for the chip.
The ground pin for all sections of the circuitry
except the oscillator and oscillator related
circuitry.
OSC_OUT Resistive Buffered Output of the Oscillator
Inverter
OSC_DR
DIVA
OEH
3 Level input pin that selects Oscillator Drive
Level
Input used to select Binary Divide-by Option.
This pin has CMOS compatible input levels.
TRF
OUT
OSCLO_1
Active HIGH 3-STATE enable pin. This pin pulls OSCLO_2
to a high value when left floating and 3-STATEs
the output when forced low. This pin has TTL
compatible input levels.
V
CC
GND
Functional Table
Summary of Device Options
Device
3311
3312
3313
3314
3315
3316
3317
3318
3319
Divide
1, 2, 4
1, 2, 4
8, 16, 32
8, 16, 32
1, 2, 4
4
32
1, 2, 4
1, 2, 4
Enable
OEH
OEH
OEH
OEH
OEL
OEH
OEH
OEH
OEL
Drive
L, M, H
H
H
L, M, H
H
H
H
H
L, M, H
Output Rise/
Fall Time (ns)
2, 4
2, 4
4
4
1, 2
4
4
1, 2
2, 4
Each drive has one output with the choices of selecting frequency divide,
output enable, crystal drive and output rise and fall time. Crystal drive
options are:
L
=
LOW Drive
M
=
MEDIUM Drive
H
=
HIGH Drive
3
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CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319
Block Diagrams
Note: Pin numbers vary for each device
Oscillator Stage
Output Stage
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4
CGS3311 • CGS3312 • CGS3313 • CGS3314 • CGS3315 • CGS3316 • CGS3317 • CGS3318 • CGS3319
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
CC
)
DC Input Voltage Diode Current (I
IK
)
DC Input Voltage (V
I
)
DC Output Diode Current (I
OK
)
DC Output Voltage (V
O
)
DC Output Source
or Sink Current (I
O
)
Storage Temperature (T
STG
)
Junction Temperature (T
J
)
SOIC
140°C/W
±70
mA
−55°C
to 150°C
−0.5V
to 7.0V
±9
mA
−0.5V
to 7.0V
±20
mA
-0.5V to V
CC
+
0.5V
Recommended Operating
Conditions
Supply Voltage (V
CC
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Operating Temperature (T
A
)
4.5V to 5.5V
0V to 5.5V
0V to V
CC
V
−40°
to
+85°C
Note 1:
The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the DC and AC
Electrical Characteristics tables are not guaranteed at the absolute maxi-
mum ratings. The Recommended Operating Conditions will define the con-
ditions for actual device operation.
DC Electrical Characteristics
T
A
= +25°C
V
CC
Symbol
V
IHTTL
Parameter
Minimum HIGH Level
Input Voltage,
TTL Level Inputs (OEH, OEL)
Maximum LOW Level
Input Voltage, TTL Level
Inputs (OEH, OEL)
Minimum HIGH Level
Input Voltage. CMOS
Level Inputs (DIVA)
Maximum LOW Level
Input voltage. CMOS
Level Inputs (DIVA)
Minimum Logic 1 Input
for Three Level Input
(DIVB, OSC_DR)
Minimum Logic 1/2 Input
for Three Level Input
(DIVB, OSC_DR)
Maximum Logic 0 Input
Level Three Level Input
(DIVB, OSC_DR)
Minimum HIGH Level
Output Voltage
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
V
OL
Minimum LOW Level
Output Voltage
4.5
5.5
4.5
5.5
I
IHRES
Input Current for Pins
DIVB, OSC_DR, and
DIVA (Input is Logic HIGH)
Input Current for Pins
DIVB, OSC_DR, and
DIVA (Input is Logic LOW)
Input Current for
Enable Pin OEL
Input Current for
Enable Pin OEH
Input Current for OSC_IN Pin
(Indicates Bias Resistance)
Input Current for OSC_IN Pin
(Indicates Bias Resistance)
Output Disabled Current
(Output HIGH)
5.5
220
0.001
0.001
4.49
5.49
4.40
5.40
3.86
4.86
0.1
0.1
0.44
0.44
360
200
3.15
3.85
1.35
1.65
4.05
4.95
1.8
2.2
2.7
3.3
0.45
0.45
4.40
5.40
3.76
4.76
0.1
0.1
0.44
0.44
380
µA
I
OL
= +48mA
V
IN
=
V
IL
or V
IH
V
IN
=
5.5V
V
I
OH
= −48
mA
V
IN
=
V
IH
or V
IH
I
OUT
=
50µA
Typ
Guaranteed Limits
Min
2.0
2.0
0.8
0.8
3.15
3.85
1.35
1.65
4.05
4.95
1.8
2.2
2.7
3.3
0.45
0.45
V
I
OUT
= −50µA
V
V
V
V
Max
Min
2.0
2.0
0.8
0.8
V
V
Max
Units Conditions
V
T
A
= −40°
C to
+85°C
V
ILTTL
V
IHCMOS
V
ILCMOS
V
IN3L_H
V
IN3L_1/2
V
IN3L_L
V
OH
I
ILRES
5.5
−220
−360
−200
−380
µA
VIN
=
0.0V
I
IHENAB
I
ILENAB
I
IHOSC
I
ILOSC
I
OZH
5.5
5.5
5.5
5.5
4.5
5.5
90
−90
20
−20
160
−160
100
−100
3.0
3.0
85
−85
20
−20
175
−175
125
−125
5.0
5.0
µA
µA
µA
µA
µA
V
IN
=
5.5V
V
IN
=
0.0V
V
IN
=
5.5V
V
IN
=
0.0V
V
OUT
=
V
CC
5
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