CD40 series chipsCD40 series chip data, CD4000: Dual three-input NOR gatesCD4001: Quad dual-input NOR gatesCD4002 Dual four-input NOR gatesCD4006: 18-bit static shift register//When D1 is high (low), clk gives four pulses D1+4 is high (low), which is equivalent to delaying four pulsesCD4007: Dual complementary pair invertersCD4008: Parallel carry output full adderCD4009: Six phase retarder/conversion-invertingCD4010: Six phase retarder/conversion-positiveCD4011 Quad 2-input NAND gatesCD4012 Dual 4-input NAND gatesCD4013 Dual master-slave D-type flip-flopsCD4014 8-bit serial-in/parallel-in-serial-out shift registerCD4015 Dual 4-bit serial-in/parallel-out shift registerCD4016 Quad transmission gatesCD4017 Decimal counter/distributorCD4018 Prefabricated 1/N counter // When PE is high, input data in parallel, regardless of clk. When PE is low, input D and shift CD4019, four-AND or selector CD4020, 14-stage serial binary counter/divider clk gives eight falling edges Q3 to start counting
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