This paper establishes a performance analysis model of the on-chip network for application design, and on this basis proposes an on-chip cache optimization strategy and allocation algorithm. The simulation on the hardware implementation platform shows that the on-chip network analysis model established in this paper can well analyze the on-chip network communication delay and the blocking probability of routing nodes in each direction, so as to optimize the cache resources of the on-chip network, reduce the average delay of data passing through the network under the same cache resources, and improve the performance of the on-chip network.
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