Design of frame transceiver for multifunctional vehicle bus controller chip

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Design of frame transceiver for multifunctional vehicle bus controller chip [Copy link]

1 Introduction
With the development of embedded microcomputer control technology and fieldbus technology, the process control of modern trains has developed from a centralized direct digital control system to a network-based distributed control system. MVB (Multi-function Vehicle Bus) based on distributed control is the recommended solution of IEC61375-1 (1999) TCN (International Standard for Train Communication Network). The train communication bus composed of MVB and WTB (Twisted Wire Train Bus) has the characteristics of strong real-time performance and high reliability. The development trend of modernization of train vehicles and the requirements of reliability, safety and real-time communication make MVB gradually become the communication bus standard for the next generation of vehicles.
MVB is a serial data communication bus mainly used for interconnected devices with interoperability and interchangeability requirements. In addition to vehicle communication, it can also be used as other fieldbuses.
MVB and MVBC are inseparable. MVBC (Multi-function Vehicle Bus Controller) is a new generation of core processors on the MVB bus. It is independent of the physical layer and functional devices and provides communication interfaces and communication services for each device on the bus. MVBC has greatly improved in performance compared with the previous generation MVB communication controller BAP15-2/3 and is currently the most advanced communication controller on the MVB bus.
The MVB bus is connected to the MVBC through a bus adapter. According to IEC-61375, the Manchester code is used on the MVB bus, and an 8-bit CRC check code is added after every 64-bit frame data. The MVB frame is divided into a master frame and a slave frame, which are composed of a frame header, data, a check code and a frame tail, respectively. The types of different frames are distinguished by the frame header.
The data communication between the MVB and the MVBC is completed by the frame transceiver in the MVBC, including the control of frame sending and receiving, Manchester encoding and decoding, and the generation of CRC check codes and data verification. The frame transceiver plays the role of the underlying data processing of the data link layer in the MVBC, which is one of the design difficulties of the MVBC chip. The design and implementation of this module plays an important role in the development of the entire MVBC.
This article mainly introduces the algorithm and implementation method of the frame transceiver module located at the physical layer interface of the MVBC bus.
2 Introduction to MVBC
MVBC can be configured to be applied in Class 1, 2, 3, and 4 devices of the IEC.TCN standard. The bus connects programmable on-board electronic devices, as well as some simple sensors and actuators, and can address up to 4096 devices.
MVBC converts the serialized signal from the MVB bus into parallel data bytes, and also sends the bytes to be sent to the transmission medium through the serialization circuit. MVBC can realize the functions of bus master and bus slave according to the configuration, realize the data processing of the data link layer and part of the transmission layer, and interact with the upper layer software through the communication memory. The bus controller contains the encoding/decoding circuit and the logic circuit required to control the communication memory, which is used to control the sending and receiving of frames (such as conflict detection, frame leading bit processing, CRC check bit processing, etc.); decode the input frame and check its validity; store the data in the corresponding communication memory.
3 Design of frame transceiver
The frame transceiver in MVBC is mainly responsible for the sending and receiving of frames, including Manchester code encoding and decoding, CRC (cyclic redundancy check code) generation and verification, construction and identification of different types of frames, and identification of code errors and conflict detection. Among them, Manchester encoding and decoding and CRC verification are the main algorithms.
3.1 Design of Manchester Encoder and Decoder
The serial data on the MVB bus adopts Manchester code. Each data bit in Manchester code is encoded according to the following specifications:
a) The encoding of a "1" is "high" in the first half of the bit and "low" in the second half;
b) The encoding of a "0" is "low" in the first half of the bit and "high" in the second half;
as shown in Figure 2-4:
If the entire bit is high (NH) or low (NL) in the Manchester code, it is considered as a non-data symbol and is used in special occasions, such as: frame header and frame end mark.
(1) Manchester encoder
According to the encoding requirements of Manchester code, the circuit implementation of Manchester encoder is shown in Figure 2-5:
The serial data is output from the shift register of the previous level at the rising edge of the 1.5M clock, and is XORed with the 1.5M clock at high and low levels, resulting in a Manchester code that conforms to the above encoding rules.
(2) Manchester decoder The
Manchester decoding process mainly converts the serial Manchester code into a serial level signal, and combines the serial level signal into a parallel signal output for further processing. If the input codeword does not conform to the Manchester code encoding rules (caused by conflict or other reasons), the decoder will report an error message. The
Manchester decoder design circuit is shown in Figure 3-3:
After the Manchester code is input, it is synchronized by three levels of registers to eliminate metastable states. If a falling edge appears on the bus after the idle state, it is considered to be the start bit of the frame, and the 16-bit counter is enabled to count when a high level appears on the bus again. If each bit cycle of the Manchester code is divided into 16 parts, as shown in Figure 3-4:
the sample value obtained at data sampling 1 is the original data before Manchester encoding, and data sampling 2 is used for frame head and frame tail detection; the principle of bus conflict detection is: the level of the Manchester code on the bus within half a bit cycle should be consistent, and the levels before and after the half cycle should be different, otherwise it is considered to be a code error.
3.2 CRC Check
CRC stands for Cyclic Redundancy Check. It is an important type of linear block code with simple encoding and decoding methods, strong error detection and correction capabilities, and is widely used in the communication field to achieve error control. In various communication systems, CRC has bit-type algorithms, byte-type algorithms, and algorithms based on lookup tables. The former is suitable for serial data communication verification, and the latter two are often used in high-speed parallel communication.
MVBC can independently complete the generation of CRC check codes and data verification without software participation. Among them:
G(x) = x7+x6+x5+x2+1
In terms of circuit implementation, we choose the bit-type algorithm. The CRC generation circuit uses LFSR. The main body consists of a group of shift registers and modulo-2 adders (exclusive OR units). That is, when the data is sent serially, the data passes through the shift register with an exclusive OR unit to generate a CRC check code. The actual circuit diagram is shown in Figure 3-5:
The CRC check circuit for serial data is also the same as the CRC generation circuit. The difference is that the CRC circuit of the former is before the shift register, while the latter is after.
3.3 Design and implementation of the bus interface module
The bus interface module includes the Encoder and Decoder mentioned above.
3.3.1 Encoder
The Encoder module has the following functions:
(1) Construct frame header and frame trailer;
(2) Perform CRC check according to the instructions of the transport layer;
(3) Perform Manchester encoding on the data;
(4) Implement the transmission of master and slave frames;
In Class 1 mode and other Class modes, the encoder is controlled by the Class 1 module and the MCU respectively.
If the current configuration allows transmission, and the control module tells the encoder that there is a frame to be sent, as well as the frame type and frame length, the encoder first sends the configured frame header, then shifts the frame data and the generated CRC check code and outputs it through Manchester encoding, and finally sends the frame tail, thus completing the transmission of the master and slave frames. The circuit implementation is shown in Figure 3-6:
3.3.2 Decoder
The MVB bus uses redundant media, so MVBC requires redundant receiving modules to complete frame reception.
(1) The two decoders complete the signal detection (trust line) or redundant detection (redundant line) function according to their selection, and complete the start bit determination, data sampling, data decoding and data shifting functions of their respective frame data;
(2) The decoder receives data from the trust line and monitors the redundant line;
(3) Determine the frame type, extract the data and check sequence (non-CRC check, optional) from the frame and store them in the RXBuffer;
(4) Implement CRC check and report the receiving status.
During initialization, ICA and ICB are set as the trust line and redundant line (LAA=1) respectively. If the trust line times out, is silent, or is forced by the user, the trust line and the monitoring line are exchanged. While receiving the frame, the decoders on the ICA and ICB lines tell the line control module whether the frame is received, what type of frame, whether the reception is completed, whether the result is correct, etc. The module reports this information and which BUFFER is valid to the upper layer module for message analysis. The decoder line control diagram is shown in Figure 3-8:
4 Verification of the bus interface module
The idea of verification is to use different control signals to simulate the correctness of frame reception and transmission in different working environments: Manchester encoding, frame header, frame tail, frame data, frame type, and CRC code correctness. The verification implementation structure is shown in Figure 4-1:
the control module writes a frame of data into the Txbuffer and controls the Encoder to start sending. At this time, the frame sent by the Encoder is received by the Decoder; the control module monitors the status of the Encoder and the Decoder at the same time. When the reception is completed, the control module reads the received data from the Rxbuffer and verifies the properties of the frame from the receiving status of the Decoder: whether the frame is valid, the frame type, the frame length, and verifies the correctness of the data from the read data.
5 Conclusion
The MVB bus will be widely adopted with the widespread application of the next generation of train communication systems, and MVBC will also have huge market prospects. This article mainly introduces the algorithm analysis, design implementation and verification scheme of the frame transceiver module of the MVBC and MVB bus interface. Through the author's recent FPGA verification of this module, the feasibility of the design work and verification scheme is fully demonstrated.