How bus transceivers use bidirectional buffers

Transceivers use back-to-back tri-state buffers to connect different devices to a common communication bus that shares bidirectional data.

    A transceiver can be used to provide bidirectional, input or output control, either digital or analog devices to a common shared data bus. Unlike buffers, transceivers are bidirectional devices, allowing data to flow through them in either direction.

    Hence, their name "transceiver" is a portmanteau from the merger of two words, trans-mitter and re-ceive (transmitter/receiver). Transceivers are also known as: send/receive or driver/receive devices.

    A buffer does not perform an inverting or decision making function, unlike a digital logic gate with two or more inputs, but produces an output condition that exactly matches the conditions of the inputs. Thus, a buffer is a "non-inverting" device that produces the Boolean expression: Q = A.

    Digital Buffer

    A digital buffer like the one shown, is a unidirectional device, i.e. the signal passes through them in one direction only, from the input "A" to the output "Q".

    Therefore, for a positive logic device (such as the CMOS 74HC4050), when input A is logic "1", output Q is logic "1", and when input A is logic "0", output Q is logic "0" for the hexadecimal buffer gate.

    Buffers can be used to isolate other gates or circuit stages from each other to prevent the impedance or operation of one circuit from affecting the impedance or operation of another circuit. Likewise, buffers can also be used alone as drivers for high current loads such as transistor switches, since their output drive capability (fan-out) is usually much higher than their input signal requirements. For example, the TTL74LS07 is a hexadecimal buffer/driver with open collector, high voltage (30 volt) outputs.

    TTL74LS07 Digital Buffer

    The digital non-inverting buffer function can also be implemented using spare logic AND or logic OR gates or using pairs of NOT gates (inverters) as shown.

    Equivalent buffer design

    One of the disadvantages of a single input digital buffer is that the output at Q will always be at the same logic level as the input, which may affect any circuit or device connected to the buffer's output terminals. One way to solve this problem is to convert the basic buffer into a three-state buffer (commonly called a tri-state buffer).

    "Tri-state buffer"

    A tri-state buffer is another type of buffer circuit that can be used to control the passage of logic signals from its input to its output. A tri-state buffer is a combinational device whose output can be electronically turned "on" or "off" by an external "control" or "enable" (EN) signal input, allowing it to be used in bus-oriented systems.

    As the name implies, the "Q" output of a tri-state buffer can assume one of three possible states, logic "0", logic "1", and High-Z (high impedance), i.e., an open circuit, instead of the standard "0" and "1" states.

    The buffer enable or control signal can be either a logic “0” or logic “1” level signal and its output is inverting and non-inverting when the digital signal passes through it. The two most commonly used tri-state buffer ICs are the TTL74LS125 and TTL74LS126.

    Therefore, a tri-state buffer requires two inputs. As shown in the figure, one is the data input (A) and the other is the control or enable input (EN).

    Three-state buffer switch equivalent

    The symbol for a tri-state buffer is very similar to the standard buffer symbol above, but with the addition of a second input representing the enable/disable control function. When the enable (EN) input is at logic level "1" (for positive logic), it acts as a normal buffer, allowing the input signal A to pass directly to the output at Q regardless of whether it is a logic "0" or a logic "1".

    When the enable input is at logic '0', the tri-state buffer is activated to the third state and disables or turns off its output, creating an open circuit condition. The third condition is neither a logic '1' (high) nor a logic '0' (low), but instead gives the output state at a very high impedance, High-Z, often written as: Hi-Z.

    Therefore, a tri-state buffer has two logic state inputs “0” or “1” but can produce three different output states, “0”, “1” or “Hi-Z”, which is why it is called a “tri-state” or “three-state” device. Note that this third state is not equal to a logic level “0” or “1” but a high impedance state because its output is electrically disconnected.

    We can then correctly declare an aggressively enabled tri-state buffer:

    If the enable signal is logic high "1", the input signal to the buffer gate is passed directly to its output.

    If the enable signal is LOW (logic “0”), the output of the buffer gate behaves like an open circuit, i.e., high impedance (Hi-Z).

    We can display the truth table for the tri-state buffer as:

    Active "HIGH" tri-state buffer

    Tri-state buffers are available in integrated form as quad, hex, or octal buffer/drivers, such as the TTL74LS244, as shown.

    74LS244 Octal Tri-State Buffer

    Note that the eight buffers are configured as two groups of four, with the first group (A1 to A4) controlled by enable input CA and the second group (A5 to A8) controlled by enable input CB. If switching transistor loads is required, the 74LS244 has very high current sinking and sourcing capabilities.

    Tri-state buffer control

    So what can we do with a tri-state or tri-state buffer. A tri-state buffer allows multiple devices to share a common output line or bus by having only one tri-state device driving the bus at any one time while all other buffers remain in their Hi-Z state. Consider the circuit below.

    Multiple tri-state buffers on a single bus

    The output of each tri-state buffer is connected to the common line bus, but its enable input is connected to the binary decoder. The decoder guarantees that only one tri-state buffer is active at any time due to its enable signal. This allows the data of the active buffer to be passed directly onto the common bus, while the outputs of the other non-enabled buffers are effectively disconnected and placed in a high impedance state. Therefore, which buffer is connected to the common line will depend on the binary value of the decoder's select input.

    Therefore, at any given time, at most one tri-state buffer can be "active". You may have noticed that the possible combinations of different data inputs connected to one of the output lines above are similar to those of a 4-to-1 line multiplexer, and you may be right that multiplexer circuits can be easily built using tri-state buffers.

    Any tri-state buffer element can be easily converted into a normal digital buffer by simply connecting its enable (EN) input directly to +Vcc or ground, depending on the tri-state buffer being used. The output will therefore be permanently enabled, so any input signal appearing at "A" will pass directly through the buffer to the output at "Q".

    So far we have seen that we can use tri-state buffers to send information in a unidirectional manner onto a common wire or bus. But how can we use them to send data in both directions i.e. also send data and receive data from a common wire bus.

    Bidirectional buffer control

    It is also possible to connect the tri-state buffers "back to back" (in anti-parallel) to create what is known as a bidirectional buffer or transceiver circuit. As shown in the figure, by using an additional inverter, one tri-state buffer acts as an "active high buffer" while the other tri-state buffer acts as an "active low buffer".

    Multiple tri-state buffers on a single bus

    Here, two tri-state buffers are connected in parallel with the enable control input but inversely connected from "A" to "B", with EN acting more like a direction control signal, thus allowing data to be read "from" and sent "to" to the same data terminal.

    So, in this simple example, when the enable input is high, (EN equals logic "1") data is allowed to pass from A to B through buffer 1, and when the enable input is low, (EN equals logic "0") data passes from B to A through buffer 2.

    Therefore, the enable input "EN" is used as a direction control, allowing data to flow in either direction depending on the logic state of this control input. In this type of application, a tri-state buffer with bidirectional switching capability (such as the TTL74LS245 or the inverting CMOS74ALS620) can be used to produce a so-called bus transceiver.

    Bus transceiver

    A bus transceiver is a three-state bidirectional device that allows data flow between two points, making it compatible with bidirectional (input or output) control of bus-oriented systems or interface circuits. A bus transceiver can be an inverting device such as the TTL74LS242 or a non-inverting device such as the TTL74LS243.

    So we can connect any input/output device to an 8-bit data bus using an 8-wire octal transceiver, with the most common bus transceiver IC used to send and receive data being the TTL74LS245 below.

    74LS245 bus transceiver

    The TTL74LS245 is an octal bus transceiver (transmitter/receiver) designed for asynchronous bidirectional communication between two data buses or input/output devices. The transceiver allows data to be transferred from terminal A to terminal B or vice versa depending on the logic level on the direction control (DIR) input (pin 1).

    Thus, for example, if the direction control input is HIGH at a logic level "1", data will be passed from terminal A to terminal B. If the direction control input is LOGICAL LEVEL "0", data will be input LOW. When held HIGH at a logic level "1", the output Chip Enable (CE) input (pin 19) can be used to disable the device, thereby enabling the terminal and therefore all connected data buses to be effectively isolated from each other.