Design of test system for multifunctional memory chip

With the rapid development of electronic technology, the types of memory are becoming more and more diverse, and each memory has its own unique operation timing. In order to improve the test efficiency of memory chips, a multifunctional memory chip test system has emerged. This paper proposes a hardware design and implementation of a multifunctional memory chip test system, and carries out detailed node circuit design (how to mount on the NIOSII bus) for various memory chips with various data bit widths (SRAM, MRAM, NOR FALSH, NAND FLASH, EEPROM, etc.), and finally solves the same platform test solution for multiple memories with different data bit widths, and designs the hardware implementation method of each node in detail.

introduction

With the rapid development of electronic technology, there are more and more varieties of memory chips, and their operation methods are completely different. Therefore, to test one type of memory chip, there will be a dedicated memory chip tester. The various memory chip test system designed in this paper can perform functional tests on various memory chips such as SRAM, Nand FLASH, Nor FLASH, MRAM, EEPROM, etc., and each type is compatible with data buses of different widths such as 8 bits, 16 bits, 32 bits, and 40 bits. If a test platform is designed separately for each product, the complexity of the test operation can be imagined. In order to simplify the test steps, reduce the complexity of the test, improve the test efficiency, and reduce the test cost, a multifunctional memory chip test system is specially designed to achieve convenient and fast testing of all the above memory chips on the same platform.

Design Principle

This design scheme adjusts the external bus timing of NIOSII appropriately based on the read and write timing access characteristics of the above-mentioned various memories through the flexible programming characteristics of FPGA, and finally realizes the precise operation of the read and write timing of various memories accessed by the external bus based on NIOSII. As shown in Figure 2-1. Through FPGA, a bus interface-ABUS that can mount all memory chips is customized, as shown in Table 1. Moreover, various connected memory chips under test can be automatically identified on the same interface. They are distinguished by the category input signal (CLAS), and each memory chip corresponds to a unique operation timing. The following are the interface connection methods and signal descriptions of several memory chips. Other memory chips can be mounted on the ABUS bus in a similar way to complete the test.

40-bit NAND FLASH connection design

As shown in Figure 2-2, the 40-bit NAND FLASH and NIOSII are bridged by ABUS (FPGA), which completely converts the timing of the external bus into the operation timing of NAND FLASH. The 40-bit NAND FLASH chip is composed of five independent 8-bit NAND FLASH chips. The external IO ports of the five 8-bit devices are spliced ​​into a 40-bit external IO port, and their respective control lines (NCLE, NALE, NRE, NWE) are connected together to form a group of control lines (NCLE, NALE, NRE, NWE). The chip selects are independently led out to NCS0-NCS9, and the busy signals are independently led out to R/B0-R/B9.

Table 2 details the connection relationship between 40-bit NAND FLASH and ABUS.

40-bit SRAM connected to NIOSII

The 40-bit SRM module is connected to NIOSII through ABUS to achieve correct timing read and write operations. During the test, only 8 bits are tested at a time, and the test of all spaces is completed in 5 times. See Figure 2-4. Table 4 is a detailed signal connection description.

8-bit SRAM connected to NIOSII

The 8-bit SRM module is connected to NIOSII through ABUS (FPGA) to achieve correct timing read and write operations, as shown in Figure 2-5. Table 5 is a description of the signal connection.

The 8-bit SRM module is connected to NIOSII through ABUS (FPGA) to achieve correct timing read and write operations, as shown in Figure 2-5. Table 5 is a description of the signal connection.

Hardware circuit design

When testing NAND FLASH, the test time can be as long as ten hours. In order to improve the test efficiency and increase the test speed, this design uses two sets of completely identical and independent hardware systems. Up to 2 NAND FLASH devices can be tested at the same time. Each hardware system consists of three modules: a microprocessor (NIOSII) plus a large-capacity FPGA and a memory test expansion interface (i.e., ABUS interface). As shown in Figure 3-1. The RS232 communication interface realizes data exchange between the test system and the host computer and completes human-computer interaction. The power supply system generates various suitable voltages to meet the power supply of each chip.

Processor module circuit

The processor module circuit consists of the NIOSII soft core (CPU) embedded in the FPGA, two RS232 communications, a FLASH chip and an SRAM chip. The CPU is the core manager of the entire system, responsible for the read and write tests of various memory chips downwards, and responsible for communicating with the host computer upwards to achieve human-computer interaction. The communication is completed by one of the RS232 circuits, and the other RS232 circuit is used to implement system debugging and software curing. The FLASH chip is used to store program code and important data. After the CPU is powered on, the SRAM chip loads the FLASH program through the CPU, and finally provides a fast running environment for the CPU program code.

ABUS interface module based on FPGA

The ABUS interface module consists of an FPGA chip, a configuration FLASH, and a data storage EEPROM chip. ABUS is used to connect the external bus of NIOSII with various memory modules. Each specific memory has a specific timing logic, and each timing logic can be implemented through the hardware code (IP core) of the FPGA. During the test, each specific memory module will give the ABUS interface a fixed category signal CLAS. The ABUS interface identifies various SIP memory modules based on this category signal, and finally switches out the correct timing logic corresponding to the specific product to complete the read and write test of the memory chip by NIOSII through the external bus. The configuration FLASH realizes the loading of the hardware program when the FPGA is powered on and the power-off data protection. EEPROM is used to store some important system parameters.

SIP memory test extension interface

The memory test expansion interface consists of two rows of double-row sockets in hardware. There are 120 pins in total. The ABUS interface is connected to the test expansion interface: 40 pins are connected to bidirectional data or I/O lines, 8 pins are connected to 8 signal input control lines, 16 pins are connected to 16 chip select signal output lines, 5 pins are connected to 5 category input signals, 16 pins are connected to 16 status input signal lines, and 27 pins are connected to 27 address lines. Other pins can be allocated to power and ground lines, as well as signal indications, etc.

Design of ABUS Interface IP Core

Each SIP memory corresponds to a specific ABUS interface IP core to achieve the correct timing read and write operations. This IP core has a unified interface convention, which is composed of two fixed interfaces. The external bus interface connected to NIOSII is implemented according to the external bus timing specification of NIOSII. The other interface is the ABUS interface mentioned above. When the corresponding CLAS signal is valid, it is responsible for converting the external bus read and write timing of NIOSII into the timing of the corresponding memory chip. The job of the IP core is to complete the conversion of these read and write operations. Table 5 shows the class signal (CLAS) input values ​​corresponding to various SIP memories. When designing the interface adapter board, this value must be set so that ABUS will switch out the correct read and write timing.

The meaning of the seven-bit category identification signal is: T_XX_WW_CC, T is 1 for high and low test, and 0 for functional test at room temperature. XX indicates the memory type, WW indicates the bus width, and CC indicates the capacity type.

8-bit SRAM/MRAM/NOR FLASH interface IP core design

As shown in Figure 4-1, the interface operations of SRAM, MRAM and NOR FLASH are basically the same, and the bus timing of NIOSII is fully satisfied. Therefore, in the FPGA, it is only necessary to simply connect the corresponding control lines and data lines, and only a chip select register needs to be designed to distinguish the 16 chip selects of the memory chip. Each chip select can access 128MByte of space. The address of the chip select register is (base address + 0x0FFFFFFC), and the base address is set at the highest address bit of the NIOSII external bus.

16-bit SRAM/MRAM/NOR FLASH interface IP core design

As shown in Figure 4-2, the interface operations of SRAM, MRAM and NOR FLASH are basically the same, and the bus timing of NIOSII is fully satisfied. Therefore, in the FPGA, it is only necessary to simply connect the corresponding control lines and data lines, and only a chip select register needs to be designed to distinguish the 16 chip selects of SIP. Each chip select can access 128MByte of space. The address of the chip select register is (base address + 0x0FFFFFFC), and the base address is set at the highest address bit of the NIOSII external bus.

32-bit SRAM/MRAM/NOR FLASH interface IP core design

As shown in Figure 4-3, the interface operations of SRAM, MRAM and NOR FLASH are basically the same, and the bus timing of NIOSII is fully satisfied. Therefore, in the FPGA, it is only necessary to simply connect the corresponding control lines and data lines, and only a chip select register is needed to distinguish the 16 chip selects of SIP. Each chip select can access 128MByte of space. The address of the chip select register is (base address + 0x0FFFFFFC), and the base is set at the highest address bit of the NIOSII external bus.

40-bit SRAM/MRAM/NOR FLASH interface IP core design

As shown in Figure 4-4, the 40-bit data width is a bit special. Here we divide the 40-bit data into five 8-bit areas and use an 8-bit bus to access each area separately. The bit select register in the IP core is used to switch the 8-bit data bus to one of the five areas of the 40-bit bus. The address of the chip select register is (base address + 0x0FFFFFFC), and the address of the bit select register is (base address + 0x0FFFFFF8). The maximum memory SRAM/MRAM/NOR FLASH module that can be tested is 128M & TI mes; 40-bit & TI mes; 16 chips.

8-bit NAND FLASH ABUS interface IP design

As shown in Figure 4-5, one of the 16 chip selects of the module is selected by writing the chip select register. We agree that its address is (base address + 0x0FFFFFFC). Reading the status register returns the busy signals of 16 NAND FLASH chips, and its address is (base address + 0x0FFFFFF8). Writing data to the address (base address + 0x00) is a write operation to the NAND FLASH data register. Reading data from the address (base address + 0x00) unit is a read operation to the NAND FLASH data register. Writing data to the address (base address + 0x01) is a write operation to the NAND FLASH command register. Writing data to the address (base address + 0x02) is a write operation to the NAND FLASH address register.

16-bit NAND FLASH ABUS interface IP design

16-bit NAND FLASH memory chips can be combined in many ways, including multiple 16-bit NAND FLASH combinations or multiple 8-bit NAND FLASH combinations. Here we assume that the 16-bit SIP NAND FLASH product is composed of multiple 16-bit NAND FLASH combinations, and the following IP core is designed based on its structure.

As shown in Figure 4-6, one of the 16 chip selects of the module is selected by writing the chip select register. We agree that its address is (base address + 0x0FFFFFFC). Reading the status register returns the busy signals of 16 NAND FLASH chips, and its address is (base address + 0x0FFFFFF8). Writing data to the address (base address + 0x00) is a write operation to the NAND FLASH data register. Reading data from the address (base address + 0x00) unit is a read operation to the NAND FLASH data register. Writing data to the address (base address + 0x01) is a write operation to the NAND FLASH command register. Writing data to the address (base address + 0x02) is a write operation to the NAND FLASH address register.

Verification and summary

After writing the written FPGA program and debugged C code into FLASH, the FPGA is reconfigured after power-off. The output of the serial port can normally identify all the set memory chips and can accurately perform read and write function tests. The design purpose has been achieved.

This article introduces a low-cost, simple, and flexible hardware design for a variety of memory chip test systems, and uses FPGA, FLASH, SDRAM, RS232 circuits, etc. With this solution, users can flexibly increase the test system functions according to market demand and implement more memory chip tests.